PSB 21473 F V1.3

D at a S h e e t , D S 1 , M ar . 2 00 3 INCA-D Infineon Codec with DASL Transceiver and embedded Microcontroller Featuring Acoustic Echo Cancellation PSB 21473 Version 1.3 Wire d Communications N e v e r s t o p t h i n k i n g . INCA-D PSB 21473 • Data Sheet Revision History: 2003-03-31 DS 1 Previous Version: 02.01 / Data Sheet DS3 Page Subjects (major changes since last revision) 52/ 173 Reset value of SYSCON modified 74 Table entries deleted 103 HDLEN bit of register PSW removed 174 Reset value of BUSCON0 corrected 181 Reset value of WDTCON corrected 232 S0CON.RXDI bit moved to position 5 407 Peak Detector has no output 420 Note for PIDDHWCFG added 421ff Modified formulas marked by vertical change bars 507 DSP register descriptions moved 508 Description of keyscanner interrupt generation modified 515 14 interfaces and 6 Alternate settings supported (see vertical change bars) 516 Description regarding physical vs. logical endpoints modified 516 Figure for Configuraton 0 added 550 Bit position of AIM and IWIE 559 Description of CIAR modified 560 Reset of bits in GEPIR 562 Two bits in register CIARIE added 566 Device Detach Interrupt not available 567 Description for SUI modified 583 Sleep mode description modified 608 Reset values adapted 633 Absolute Maximum Ratings modified 634ff DC characteristics modified 656 DC characteristics of transceiver removed (informaton partly moved to DC char.) 659ff Values for ADC charateristics modified, transmission characteristics for AFE Data Sheet 2 DS 1, 2003-03-31 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. Edition 2003-03-31 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 11/23/04. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. INCA-D PSB 21473 Table of Contents Page 1 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.1.9 1.1.10 1.1.11 1.2 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bit CPU, Internal RAM and Memory Interface . . . . . . . . . . . . . . . . . General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . . . . . . Two Serial Channel Interfaces (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bit fixed-point DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Specific Functions (TSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 3.1 3.2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bus Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Specific Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller and Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description of the Clock Concept Unit . . . . . . . . . . . . . . . . . . . . . 33 34 35 35 35 36 38 38 39 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal ROM (Bootstrap Loader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Chip XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Dual-Port-RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . XBUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 41 41 41 42 43 43 44 45 46 Data Sheet 4 14 15 15 15 16 16 16 16 17 17 17 17 17 18 19 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents Page 5.10 Crossing Memory Boundaries 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PEC - Extension of Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XBUS System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XBUS Peripheral Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.1 Integrated OCDS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Applications of OCDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Combined Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Node 3 (USBINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt Node 4 (USBEPINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Interrupt Node 13 (COMB1INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Interrupt Node 14 (COMB2INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Normal Interrupt Processing and PEC Service . . . . . . . . . . . . . . . . . . . 98 Interrupt System Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . 107 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . 109 Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9 9.1 9.1.1 9.2 9.2.1 9.3 9.3.1 9.4 9.4.1 9.5 9.5.1 9.6 9.6.1 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Functions of PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Functions of PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Functions of PORT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Functions of PORT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Functions of PORT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PORT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Functions of PORT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 48 49 51 70 77 77 80 123 127 131 132 136 136 139 141 144 146 148 149 151 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents Page 9.7 9.7.1 PORT7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Alternate Functions of PORT7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 10 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11 11.1 11.2 11.3 11.4 The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12.1 The Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13 13.1 13.2 13.3 The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Activation of ASC Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer of User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 183 185 186 14 14.1 14.1.1 14.1.2 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.3 General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description of Timer Block 1 . . . . . . . . . . . . . . . . . . . . . . . . . Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . . . Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the GPT Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 188 189 198 205 206 209 211 217 218 15 The Asynchronous / Synchr. Serial Interface . . . . . . . . . . . . . . . . . . . 15.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.4 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5.3 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5.4 IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.5.5 RXD/TXD Data Path Selection in Asynchronous Modes . . . . . . . . . 15.1.6 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.6.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.6.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 229 229 229 231 237 237 238 241 242 242 244 244 245 246 Data Sheet 6 159 160 168 172 178 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents 15.1.6.3 15.1.7 15.1.7.1 15.1.7.2 15.1.8 15.1.9 Page Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baudrates in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Baudrates in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 247 248 251 253 253 16 16.1 16.2 16.3 16.4 16.5 The High-Speed Synchronous Serial Interfaces . . . . . . . . . . . . . . . . . Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSCx Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 262 265 267 268 270 17 17.1 17.1.1 17.1.2 17.1.2.1 17.1.3 17.1.4 17.1.5 17.1.5.1 17.1.6 17.1.7 17.1.8 17.1.8.1 17.1.8.2 17.1.9 17.2 17.2.1 17.2.2 17.2.3 17.2.4 17.3 17.3.1 17.3.2 17.3.3 17.3.3.1 17.3.3.2 17.3.3.3 17.3.4 17.3.5 IOM-2 Handler, TIC/CI Handler and HDLC Controller . . . . . . . . . . . . . IOM2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Looping and Shifting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data transfer from and to the IOM-2 bus . . . . . . . . . . . . . . . . . . . . . . . Data Access on IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compare Feature for transfer unit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . Communication between DSP and IOM-2 . . . . . . . . . . . . . . . . . . . . . . Serial Data Strobe Signal and strobed Data Clock . . . . . . . . . . . . . . . Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strobed IOM Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIC/CI Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIC Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIC Bus Handler - Functional Description . . . . . . . . . . . . . . . . . . . . . . HDLC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Possible Error Conditions during Reception of Frames . . . . . . . . . . Data Reception Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 271 272 273 275 279 280 283 283 287 288 289 289 290 291 291 291 292 292 293 295 295 295 298 298 301 301 304 305 Data Sheet 7 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents Page 17.3.5.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.5.2 Possible Error Conditions during Transmission of Frames . . . . . . . 17.3.5.3 Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.5.4 Transmit Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.6 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.6.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.6.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4 HDLC Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1 HDLC Control and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.1 RFIFO - Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.2 XFIFO - Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.3 ISTAH - Interrupt Status Register HDLC . . . . . . . . . . . . . . . . . . . . . 17.5.1.4 MASKH - Mask Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.5 STAR - Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.6 CMDR - Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.7 MODEH - Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.8 EXMR- Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.9 SAP1 - SAPI1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.10 RBCL - Receive Frame Byte Count Low . . . . . . . . . . . . . . . . . . . . . 17.5.1.11 SAP2 - SAPI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.12 RBCH - Receive Frame Byte Count High . . . . . . . . . . . . . . . . . . . . 17.5.1.13 TEI1 - TEI1 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.14 RSTA - Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.15 TEI2 - TEI2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.16 TMH -Test Mode Register HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1.17 CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . 17.5.1.18 CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . 17.5.1.19 CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . 17.5.1.20 CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . 17.5.2 IOM Handler (CDA) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.2.1 CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . 17.5.2.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . 17.5.2.3 CDAx_CR - Control Register Controller Data Access CH1x . . . . . . 17.5.3 IOM Handler (Control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.3.1 TR_CR - Control Register Transceiver Data . . . . . . . . . . . . . . . . . . 17.5.3.2 BCHx_CR - Control Register B-Channel Data . . . . . . . . . . . . . . . . 17.5.3.3 DCI_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . . 17.5.3.4 DCIC_CR - Control Register for HDLC and CI1 Data . . . . . . . . . . . 17.5.3.5 SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . 17.5.3.6 IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . 17.5.3.7 STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 8 305 307 307 309 310 310 310 311 312 318 318 318 318 320 320 321 322 323 325 325 325 326 326 327 328 329 329 330 331 331 332 332 332 333 335 335 335 336 336 337 338 339 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents Page 17.5.3.8 ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . 17.5.3.9 MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . 17.5.3.10 SDS_CONF - Configuration Register for Serial Data Strobes . . . . . 17.5.3.11 MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6 Interrupt and General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.1 ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.2 MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.3 MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.4 ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.5 SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.6 IOM Handler (Transfer Units) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6.6.1 ITRDU - IOM Transfer Unit, Read/Write Register DU . . . . . . . . . . . 17.6.6.2 ITRDD - IOM Transfer Unit, Read/Write Register DD . . . . . . . . . . . 17.6.6.3 ITRICV - IOM Transfer Unit, Idle Code Value for transfer unit 0 . . . 17.6.6.4 ITR_CR - IOM Transfer Control Register Register . . . . . . . . . . . . . 17.6.6.5 ITR_MSK0 - IOM Transfer Time Slot and Data Port Sel. Reg. 0 . . . 17.6.6.6 ITR_MSKx - IOM Transfer Time Slot and Data Port Sel. Reg. 1 - 7 17.6.6.7 IWSR - IOM waitstates register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 340 341 341 341 341 342 343 343 344 344 344 345 345 345 346 347 347 18 18.1 18.2 18.3 18.4 18.4.1 18.4.1.1 18.4.1.2 18.4.1.3 18.4.1.4 18.4.1.5 18.4.2 18.5 18.6 18.7 18.7.1 18.7.2 18.8 18.9 18.9.1 18.9.2 18.9.3 18.9.4 18.9.5 349 349 349 350 351 353 353 356 357 357 358 358 359 359 360 360 360 360 361 362 362 363 363 364 Line Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wiring Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Coding, Frame Structure of the DASL interfacee . . . . . . . . . . . . . . Data Transfer and Delay between IBUS and DASL Interface . . . . . . . . . Control of Layer 1 / State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Infos on the Line (Downstream) . . . . . . . . . . . . . . . . . . . . . Transmit Infos on the Line (Upstream) . . . . . . . . . . . . . . . . . . . . . . C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level Detection and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Transceiver Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals on the Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive PLL (DPLL-Adjust Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TR_CONF0 - Transceiver Configuration Register . . . . . . . . . . . . . . . . TR_CONF1 - Receiver Configuration Register . . . . . . . . . . . . . . . . . . TR_CONF2 - Transmitter Configuration Register . . . . . . . . . . . . . . . . TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . . TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . . Data Sheet 9 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents 18.9.6 18.9.7 Page ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . . 364 MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . 365 19 19.1 19.2 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Analog Front End (AFE) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 External circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 20 20.1 20.1.1 20.1.1.1 20.1.1.2 20.1.1.3 20.1.2 20.1.3 20.1.3.1 20.1.3.2 20.1.3.3 20.1.3.4 20.1.3.5 20.1.3.6 20.1.3.7 20.1.4 20.1.5 20.1.6 20.1.7 20.1.8 20.1.9 20.1.10 20.1.11 20.1.12 20.1.13 20.1.14 20.2 20.2.1 20.2.2 20.2.2.1 20.2.2.2 20.2.2.3 20.2.3 20.3 20.4 20.4.1 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Duplex Speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echo Cancellation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echo Cancellation (Fullband Mode) . . . . . . . . . . . . . . . . . . . . . . . . . Echo Cancellation (Subband Mode) . . . . . . . . . . . . . . . . . . . . . . . . Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speech Comparators (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attenuation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echo Suppression Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Echo Cancellation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Gain Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise Reduction Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tone Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Summation Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface to IOM handler (Codec Digital Interface - CDI) . . . . . . . . . . . Parallel Interface to the DSP Domain PIDD . . . . . . . . . . . . . . . . . . . . Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restrictions and Mutual Dependencies of Modules . . . . . . . . . . . . . . . . . DSP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIDD Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 10 371 371 374 376 376 379 381 383 385 387 390 391 391 393 393 394 396 397 399 400 400 401 402 404 407 408 409 409 411 412 413 413 414 414 418 418 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents 20.4.2 20.4.3 20.4.4 Page Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 DSP address domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 21 21.1 21.2 21.3 21.3.1 21.3.2 Terminal Specific Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keypad Scanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Matrix Control for up to 24 LED’s . . . . . . . . . . . . . . . . . . . . . . . . . . . TSF Global Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keypad Scanner Register Description . . . . . . . . . . . . . . . . . . . . . . . . . LED Multiplex Unit register description . . . . . . . . . . . . . . . . . . . . . . . . 507 507 510 512 512 514 22 22.1 22.2 22.3 22.4 22.4.1 22.4.2 22.4.2.1 22.4.2.2 22.4.3 22.4.4 22.5 22.5.1 22.6 22.7 22.8 22.8.1 22.8.2 22.8.2.1 22.8.2.2 22.8.2.3 22.8.3 22.8.4 22.9 22.10 22.10.1 22.11 22.11.1 22.11.2 22.11.3 22.11.4 22.11.5 USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interruption of data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Buffer Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Buffer Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . USB block activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization of USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Device Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enumeration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Device Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GET_DESCRIPTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Onchip USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Register handling interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Register Description - USB Device Registers . . . . . . . . . . . . . . Global Endpoint Stall Register (GESR) . . . . . . . . . . . . . . . . . . . . . . . . Configuration Request Register (CIAR) . . . . . . . . . . . . . . . . . . . . . . . . Global Endpoint Interrupt Request Register (GEPIR) . . . . . . . . . . . . . Configuration Request Interrupt Register (CIARI) . . . . . . . . . . . . . . . . Configuration Request Interrupt Enable (CIARIE) . . . . . . . . . . . . . . . . 515 515 516 519 520 520 521 521 524 527 533 534 536 537 537 540 540 540 540 540 541 541 543 544 546 549 559 559 559 560 561 562 Data Sheet 11 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents Page 22.11.6 Device Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.11.7 Device Power Down Register (DPWDR) . . . . . . . . . . . . . . . . . . . . . . . 22.11.8 USB Device Interrupt Enable Register (DIER) . . . . . . . . . . . . . . . . . . 22.11.9 USB Device Interrupt Request Register (DIRR) . . . . . . . . . . . . . . . . . 22.11.10 Device Setup and Status Register (DSSR) . . . . . . . . . . . . . . . . . . . . . 22.11.11 Frame Number Register (FNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.11.12 Device Get_Status Register (DGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 22.11.13 Interface Get_Status Register (IGSR) . . . . . . . . . . . . . . . . . . . . . . . . . 22.11.14 Interface Select Registers (IFCSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . 22.11.15 Enable Setup Token(ESTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.11.16 Active Endpoint Number (ACTEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.12 Detailed Register Description - USB Endpoint Registers . . . . . . . . . . . . 22.12.1 Endpoint Get_Status Register (EGSRn) . . . . . . . . . . . . . . . . . . . . . . . 22.12.2 Endpoint Interrupt Enable Register (EPIEn) . . . . . . . . . . . . . . . . . . . . 22.12.3 Endpoint Interrupt Request Register (EPIRn) . . . . . . . . . . . . . . . . . . . 22.12.4 Endpoint Buffer Control Register (EPBCn) . . . . . . . . . . . . . . . . . . . . . 22.12.5 Endpoint Buffer Status Register (EPBSn) . . . . . . . . . . . . . . . . . . . . . . 22.12.6 Endpoint Base Address Register (EPBAn) . . . . . . . . . . . . . . . . . . . . . 22.12.7 Endpoint Buffer Length Register (EPLENn) . . . . . . . . . . . . . . . . . . . . 22.12.8 Address Offset Register (ADROFFn) . . . . . . . . . . . . . . . . . . . . . . . . . 22.12.9 USB Data Register (USBVALn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 564 565 566 567 568 569 570 570 571 571 572 572 573 574 576 577 580 581 581 582 23 23.1 23.2 23.3 23.4 23.5 23.6 Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sleep Mode of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Mode of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status of Output Pins during Idle and Power Down Mode . . . . . . . . . . . . Power Down Mode of Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Mode of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 583 584 585 586 587 590 24 24.1 24.1.1 24.1.2 24.2 24.3 24.4 24.5 24.6 24.6.1 24.6.2 24.6.3 24.7 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Lengthening Control (Start Delay) . . . . . . . . . . . . . . . . . . . . . . . . . Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset for IOM-Handler and Transceiver . . . . . . . . . . . . . . . . . . The INCA-D’s Pins after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer Operation after Reset . . . . . . . . . . . . . . . . . . . . . . . Reset and Power Down Mode of the DSP . . . . . . . . . . . . . . . . . . . . . . Ports and External Bus Configuration during Reset . . . . . . . . . . . . . . . 591 593 594 594 594 594 596 596 596 597 598 598 599 Data Sheet 12 DS 1, 2003-03-31 INCA-D PSB 21473 Table of Contents Page 24.8 System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 25 25.1 25.2 25.3 25.4 25.5 The Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . XBUS Special Function Registers ordered by Address . . . . . . . . . . . . . PD-Bus Special Function Registers ordered by Address . . . . . . . . . . . . DSP Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 606 606 608 623 630 26 26.1 26.2 26.3 26.4 26.5 26.6 26.6.1 26.6.2 26.6.3 26.7 26.8 26.9 26.10 26.10.1 26.10.2 26.10.3 26.11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . DC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics of the External Bus Interface . . . . . . . . . . . . . . . . . SSC0 and SSC1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASC Timing Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Analog Front End . . . . . . . . . . . . . . . . . . . . . . Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Front End Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Analog Front End Output Characteristics . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 633 633 634 637 637 639 640 651 652 654 656 657 659 659 661 661 662 27 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Data Sheet 13 DS 1, 2003-03-31 INCA-D PSB 21473 Overview 1 Overview The INCA-D integrates all necessary functions for the completion of a digital voice terminal solution. The line transceiver of the INCA-D implements the subscriber access functions for a digital terminal to be connected to a two wire DASL interface. It covers complete layer-1 and basic layer-2 functions for digital terminals. Different interfaces allow the connection to a variety of devices including an Full Speed USB interface for PC host communication. The basic application of the INCA-D is the use in terminal equipment applications where microphone, loudspeaker, headset or handset can be directly connected to the Analog Frontend. The Analog Front End and the integrated fixpoint DSP perform encoding, decoding, filtering functions and tone generation (ringing, audible feedback tones and DTMF signal). A full duplex echo cancellation mechanism provides high quality speakerphone functionality. The INCA-D is a CMOS device and operates with a single 3.3V supply. Data Sheet 14 2003-03-31 Infineon Codec with DASL Transceiver and embedded Microcontroller Featuring Acoustic Echo Cancellation INCA-D Version 1.3 PSB 21473 CMOS 1.1 Features 1.1.1 16 bit CPU, Internal RAM and Memory Interface • Bootstrap Loader Function • On Chip Memory: Dual Port SRAM (2 KBytes) & General Purpose SRAM (4 KBytes) • On Chip Debug System OCDS (Level 1) P-TQFP-144 • Interrupt Controller supporting up to 27 nodes • Peripheral Event Controller (PEC) for up to 8 channels • External Memory Interface supporting 8 bit or 16 bit data, multiplexed and demultiplexed • Up to 4 MBytes linear address space for external code and data • 3 programmable Chip Selects • Programmable Watchdog Timer 1.1.2 General Purpose Timer Unit Timer Block 1: • fTimer/4 maximum resolution. • 3 independent timers/counters. • Timers/counters can be concatenated. • 4 operating modes (timer, gated timer, counter, incremental). Timer Block 2: • fTimer/2 maximum resolution. • 2 independent timers/counters. • Timers/counters can be concatenated. • 3 operating modes (timer, gated timer, counter). • Extended capture/reload functions via 16-bit Capture/Reload register CAPREL. Type Package PSB 21473 P-TQFP-144 Data Sheet 15 2003-03-31 INCA-D PSB 21473 Overview 1.1.3 Asynchronous/Synchronous Serial Interface (ASC) Full duplex asynchronous operating modes • 8- or 9-bit data frames, LSB first • Parity bit generation/checking • One or two stop bits • Baudrate from 1.5 MBaud to 0.3552 Baud (@24 MHz CPU clock) • Multiprocessor mode for automatic address/data byte detection • Loop-back capability Half-duplex 8-bit synchronous operating mode • Baudrate from 3 MBaud to 305.76 Baud (@ 24 MHz CPU clock) • Double buffered transmitter/receiver 1.1.4 • • • • • • • Two Serial Channel Interfaces (SSC) Master and slave mode operation Full-duplex or half-duplex operation Flexible data format Programmable number of data bits : 2 to 16 bit Programmable shift direction : LSB or MSB shift first Programmable clock polarity : idle low or high state for the shift clock Programmable clock/data phase : data shift with leading or trailing edge of SCLK • Baudrate generation from 12 MBaud to 183.1 Baud (@ 24 MHz module clock) Interrupt generation • on a transmitter empty condition • on a receiver full condition • on an error condition (receive, phase, baudrate, transmit error) 1.1.5 • • • • • • USB Interface USB specification v1.1 compliant 12 Mbit/s Full-Speed Mode 15 Interfaces and 7 Alternate Settings supported 15 SW-configurable Endpoints, in addition to the bi-directional Control Endpoint 0 Flexible Memory Management to support Endpoint Buffer Sizes of up to 64 Bytes Each non-Control Endpoint can be either Isochronous, Bulk or Interrupt 1.1.6 16 bit fixed-point DSP • Full-duplex echo cancellation with noise reduction Data Sheet 16 2003-03-31 INCA-D PSB 21473 Overview • • • • • PCM A-Law/µ-Law (ITU-T G.711) and 8/16-bit linear data Two transducer correction filters Side tone gain adjustment Set of functional units as described (e.g. Tone Generator, DTMF Receiver) Access to two independent 16 bit time slots for up to three voice channels 1.1.7 Analog Front End • Three differential inputs for the handset, the speakerphone and the headset microphone • Three differential outputs for a handset ear piece (200 Ω), a headset (200 Ω) and a loudspeaker • 80 mW @ 25 Ω or 100 mW @ 20 Ω loudspeaker driver capability • Flexible test and maintenance loop backs in the analog front end • Gain programmable amplifiers for all analog inputs and outputs • PCM Codec, fully compatible with the ITU-T G.712 and ETSI (NET33) specification • Additional summing point to add the Tone Generator output signal and the analog converted audio output from the DSP. The result is fed to the loudspeaker. 1.1.8 Transceiver • Two wire DASL transceiver with AMI coded 2B+D channels 1.1.9 Terminal Specific Functions (TSF) • Keypad Scanner for up to 45 keys • LED Multiplex Unit (3*8 LEDs) 1.1.10 IOM-2 Handler • IOM-2 Interface • HDLC controller: Access to B1, B2 or D channels or the combination of them e.g. for 144 kbit data transmission (2B+D) • 2* 64 byte FIFO buffer for efficient D-channel transfer of data packets • Implementation of C/I-channel protocol to control peripheral devices • Test loops and functions • Data Control Unit for fast data transfers from IOM-2 time slots to memory and vice versa 1.1.11 • • • • General Features Power Management Single 15.36 MHz crystal On Chip PLL and a set of clock frequency divider 3.3V Single Supply Voltage Data Sheet 17 2003-03-31 INCA-D PSB 21473 Overview 1.2 Logical Symbols Figure 1-1 illustrates the logical symbol of the INCA-D. JTAG Interface IOM-2 Interface DD TRST TDI TMS TCK TDO Test DU FSC DCL I/O or BCL or XTAL2 XTAL1 LIa MIP1 MIN1 LIb 15.36 MHz Line Interface Analog Front End MIP2 MIN2 RSTOUT MIP3 MIN3 HOP1 HON2 RSTIN NMI HOP2 HON2 LSP LSN P7 P2 P3 BRKIN Terminal Specific Functions SSC ASC OCDS BRKOUT DPLS DMNS P0 P1 USB Figure 1-1 Data Sheet P4 Memory Interface P6 ALE RD WR logsymbol_TE.vsd Logical Symbol TE mode 18 2003-03-31 INCA-D PSB 21473 Overview 1.3 Typical Application The following figure illustrates the typical application in which the INCA-D is usually used. INCA-D Line Interface voice_te_mC.vsd Figure 1-2 Data Sheet Basic Configuration 19 2003-03-31 INCA-D PSB 21473 Pin Descriptions 2 Pin Descriptions 2.1 Pin Configuration The pin configuration of the INCA-D is shown in figure 2-1. JTAG Interface IOM-2 Interface 11 VDD 11 VSS DD TRST TDI TMS TCK TDO Test DU FSC DCL BCL XTAL2 XTAL1 VREF LIa BGREF LIb 15.36 MHz Line Interface RSTOUT RSTIN NMI P7(9:0) I/O or KEYSCAN(9:0) MIP1 MIN1 Analog Front End MIP2 MIN2 P2(0) P2(1) P2(2) MIP3 MIN3 P2(13:3) I/O or SDS1 or FEX0IN I/O or SDS2 or FEX1IN I/O or FEX2IN I/O or LEDMUX(10:0) VDD(LED) VSS(LED) HOP1 HON2 HOP2 HON2 LSP LSN BRKIN OCDS BRKOUT P3(0) I/O or MRST1 P3(1) P3(2) P3(3) P3(4) P3(5) P3(6) P3(7) P3(8) P3(9) P3(10) P3(11) P3(12) I/O or MTSR1 I/O or SCL1 I/O or T3OUT I/O or T3EUD I/O or T4IN I/O or T3IN P3(13) P3(14) P3(15) DPLS DMNS P0L(7:0) P0H(7:0) P1L(7:0) P1H(7:0) P4(5:0) USB I/O or D(7:0) I/O or D(15:8) I/O or A(7:0) P6(2:0) I/O or T2IN I/O or MRST0 I/O or MTSR0 I/O or TxD I/O or RxD I/O or BHE / WRH I/O or SCLK0 I/O or T6OUT I/O or CAPIN ALE RD WR I/O or I/O or I/O or A(15:8) A(21:16) CS Memory Interface • Figure 2-1 Data Sheet Pin Configuration 20 2003-03-31 INCA-D PSB 21473 Pin Descriptions TDO TMS TRST TEST TCK TDI VDDDPLL VSSDPLL P4.5/A21 P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 WR! RD! ALE XTAL2 XTAL1 VDD6 VSS6 P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 VDD5 The mapping of the pin configuration to the physical device is shown in figure 2-2. DPLS DMNS VSSU P6.0/CS0! P6.1/CS1! P6.2/CS2! RSTOUT! RSTIN! VSS1 VDD1 P7.0/KEYSCAN0 P7.1/KEYSCAN1 P7.2/KEYSCAN2 P7.3/KEYSCAN3 P7.4/KEYSCAN4 P7.5/KEYSCAN5 P7.6/KEYSCAN6 P7.7/KEYSCAN7 P7.8/KEYSCAN8 P7.9/KEYSCAN9 104 100 Figure 2-2 Data Sheet 96 92 88 84 80 76 73 72 112 68 116 64 120 60 124 INCA-D PSB 21473 128 56 52 132 48 136 44 140 40 144 1 4 8 P3.9/MTSR0 P3.10/TxD P3.11/RxD P3.12/BHE!/WRH! P3.13/SCLK0 VSS3 VDD3 DCL P3.0/MRST1 P3.1/MTSR1 VSS2 VDD2 P3.2/SCL1 P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST0 VSSL VDDL Lla Llb 108 109 12 16 20 24 28 32 37 36 VSS5 P1L.1/A1 P1L.0/A0 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0 VDD4 VSS4 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 P0H.0/AD8 BRKOUT! BRKIN! P2.13/LEDMUX10 P2.12/LEDMUX9 P2.11/LEDMUX8 P2.10/LEDMUX7 P2.9/LEDMUX6 HON2 HOP2 HON1 HOP1 LSN VSSP LSP VDDP BCL P3.14/T6OUT P3.15/CAPIN DU DD FSC P2.0/FEX0IN/SDS1 P2.1/FEX1IN/SDS2 VDDLED VSSLED P2.2/FEX2IN P2.3/LEDMUX0 P2.4//LEDMUX1 P2.5//LEDMUX2 P2.6/LEDMUX3 P2.7/LEDMUX4 P2.8/LEDMUX5 NMI! VDDA VSSA BGREF VREF MIN3 MIP3 MIN2 MIP2 MIN1 MIP1 VDDU Mapping of pins to physical device 21 2003-03-31 INCA-D PSB 21473 Pin Descriptions 2.2 Table 2-1 Pin No. 6269 5259 Pin Definitions and Functions Memory Interface and Control Signals Symbol Input (I) Function Output (O) Open Drain (OD PORT0 I/O (OD) PORT0 consists of the two 8-bit bidirectional I/ O ports POL and POH. It is bitwise programmable for input or output via direction bits. It contains internal pull resistors. For external memory access, PORT0 serves as the data (D) bus in demultiplexed bus modes. Beside these functions, P0 serves for latching in the start-up configuration during reset. I/O (OD) PORT1 consists of the two 8-bit bidirectional I/ O ports P1L and P1H. It is bitwise programmable for input or output via direction bits. It contains internal pull resistors. For external memory access PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes. I/O (OD) PORT4 is a 6-bit bidirectional I/O port. It is bitwise programmable for input or output via direction bits. It contains internal pull resistors. For external memory access Port4 can be used to output the segment address lines: P4.0 A16 : Least Significant Segment Address Line ... P4.5 A21: Most Significant Segment Address Line P0L.0P0L.7: P0H.0P0H.7: PORT1 70, 71, 74-79 8087 P1L.0P1L.7 P1H.0P1H.7 PORT4 P4.0P4.5 95 O ... ... O 100 PORT6 P6.0 P6.2 113 114 115 Data Sheet I/O, (OD) O O O PORT6 is a 3-bit bidirectional I/O port. It is bitwise programmable for input or output via direction bits. It contains internal pull resistors. P6.0 CS0 Chip Select 0 P6.1 CS1 Chip Select 1 P6.2 CS2 Chip Select 2 22 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-1 Memory Interface and Control Signals (cont’d) Pin No. Symbol Function Input (I) Output (O) Open Drain (OD 93 RD O External Memory Read Strobe. RD is activated for every external instruction or data read access. (internal pull-up provided) 94 WR/WRL O External Memory Write Strobe. In WR mode this pin is activated for every external data write access. In WRL mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. (internal pull-up provided) 92 ALE Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. (internal pull-down provided) Data Sheet O 23 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-2 Serial Interfaces,Terminal Specific Functions Pin No. Symbol PORT3 P3.0 P3.15 Input (I) Output (O) Open Drain (OD) I/O PORT3 is a 16-bit bidirectional I/O port. It is bit-wise (OD possible programmable for input or output via direction bits and it contains internal pull resistors. at all pins) 130 I/O 131 I/O 134 I/O 135 136 137 138 139 140 O I I I I I/O 1 I/O 2 3 4 O I/O O 5 O/I 10 11 O I Data Sheet Function The following PORT3 pins serve for alternate functions: P3.0 MRST1 Master Receive Slave Transmit SSC1 / T5IN Timer 5 Input P3.1 MTSR1 Master Transmit Slave Receive SSC1 / T4EUD Timer 4 External Up Down P3.2 SCLK1 Shift Clock SSC1 / T2EUD Timer 2 External Up Down P3.3 T3OUT Timer T3 Toggle Latch Output P3.4 T3EUD Timer T3 External Up Down P3.5 T4IN Timer T4 Input P3.6 T3IN Timer T3 Input P3.7 T2IN Timer T2 Input P3.8 MRST0 Master Receive Slave Transmit SSC0 / T6IN Timer 6 Input P3.9 MTSR0 Master Transmit Slave Receive SSC0 / T5EUD Timer T5 External Up Down P3.10 TxD ASC Data transmit P3.11 RxD ASC Data receive P3.12 BHE External Memory High Byte Enable Signal WRH External Memory High Byte Write Strobe P3.13 SCLK0 Shift Clock SSC0 / T6EUD Timer 6 External Up Down P3.14 T6OUT Timer 6 output P3.15 CAPIN GPT2 Capture Input 24 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-2 Serial Interfaces,Terminal Specific Functions (cont’d) Pin No. Symbol PORT7 P7.0 P7.9 Input (I) Output (O) Open Drain (OD) Function I/O (OD) PORT7 is an 10-bit bidirectional I/O port. It is bitwise programmable for input or output via direction bits. It contains internal pull resistors. As alternate function the following pins are used by the keyscanner P7.0 Keyscan of line 0 P7.1Keyscan of line 1 P7.2 Keyscan of line 2 P7.3Keyscan of line 3 P7.4 Keyscan of line 4 P7.5 Keyscan of line 5 P7.6 Keyscan of line 6 P7.7 Keyscan of line 7 P7.8 Keyscan of line 8 P7.9 Keyscan of line 9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 120 121 122 123 124 125 126 127 128 129 PORT2 P2.0P2.13 15 16 19 20 21 22 23 24 25 45 46 47 48 49 Data Sheet I/O (OD) I/O I/O I/O O O O O O O O O O O O PORT2 is a 14-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. It contains internal pull resistors. The following pins serve for alternate functions. P2.0 FEX0IN or SDS1 P2.1 FEX1IN or SDS2 P2.2 FEX2IN P2.3 LED multiplexing line 0 P2.4 LED multiplexing line 1 P2.5 LED multiplexing line 2 P2.6 LED multiplexing line 3 P2.7 LED multiplexing line 4 P2.8 LED multiplexing line 5 P2.9 LED multiplexing line 6 P2.10 LED multiplexing line 7 P2.11 LED multiplexing line 8 P2.12 LED multiplexing line 9 P2.13 LED multiplexing line 10 25 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-3 USB Interface Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 110 DPLS I/O USB Data+ input/output signal. 111 DMNS I/O USB Data- input/output signal. Table 2-4 IOM-2 Interface and Strobe Signals Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 13 DD I/OD/O IOM-2 Data Downstream Signal pin. For the pin configured as input, the output driver is put into high-impedance state. Open-drain. 12 DU I/OD/O IOM-2 Data Upstream Signal pin. For the pin configured as input, the output driver is put into high-impedance state. Open-drain. 14 FSC I/O Frame Synchronization Clock 8 DCL I/O Data Clock (double-bit clock) 9 BCL I/O Data Clock (bit clock) Data Sheet 26 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-5 RESET Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 117 RSTIN I Reset Input. A low level at this pin for a specified duration while the oscillator is running, resets the device. (Internal pull-up provided). 116 RSTOUT O Internal Reset Indication Output. This pin is set to a low level when the device is executing either a hardware-, software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. 26 NMI Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the CPU to go into power down mode. If NMI is high, when PWRDN is executed, the device will continue to run in normal mode. If not used, pin NMI should be pulled high externally. However, it is possible to tie NMI permanently to VSS. Table 2-6 I Boundary Scan, JTAG , OCDS Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 105 TEST I Internal Test Mode Enable (tied to VSS) 104 TCK I Test Clock Input (internal pull-up) 103 TDI I Test Data Input (internal pull-up) 108 TDO O Boundary Scan Test Data Output 107 TMS I Test Mode Select (internal pull-up) 106 TRST I Test Reset (internal pull-down) Data Sheet 27 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-6 Boundary Scan, JTAG , OCDS Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 50 BRKIN I In OCDS mode, a falling edge from HIGH to LOW signal on brkin forces the system to stop. An internal pull-up resistor is provided. 51 BRKOUT O Table 2-7 In OCDS mode, a falling edge on brkout indicates the trigger of an pre-selected OCDS event. Transceiver / XTAL Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 143 144 LIa LIb I/O I/O DASL transceiver Line Interface 91 90 XTAL2 XTAL1 O I Oscillator output Oscillator or 15.36 MHz input Data Sheet 28 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-8 Analog Front End Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function 30 VREF O 1.5V reference voltage for biasing external circuitry. 29 BGREF I Bandgap Reference Voltage 36 35 MIP1 MIN1 I I Symmetrical differential Microphone Input 1 34 33 MIP2 MIN2 I I Symmetrical differential Microphone Input 2 32 31 MIP3 MIN3 I I Symmetrical differential Microphone Input 3 41 42 HOP1 HON1 O O Differential Handset earpiece output 43 44 HOP2 HON2 O O Differential Handset earpiece output 38 40 LSP LSN O O Differential Loudspeaker output Data Sheet 29 2003-03-31 INCA-D PSB 21473 Pin Descriptions Table 2-9 Pin No. Symbol Input (I) Output (O) Open Drain (OD) Function Power supply (3.3 V −5%/+10%) 142 109 27 37 17 102 119 133 7 61 73 89 141 112 28 39 18 101 118 132 6 60 72 88 VDDL VDDU VDDA VDDP VDDLED VDDPLL VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VSSL VSSU VSSA VSSP VSSLED VSSPLL VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 Data Sheet – Supply voltage for DASL line driver – Supply voltage for USB transceiver – Supply voltage for Analog Front End – Supply voltage for loudspeaker – Supply voltage for LED mux – Supply voltage for PLL – Supply voltage 1 for digital parts – Supply voltage 2 for digital parts – Supply voltage 3 for digital parts – Supply voltage 4 for digital parts – Supply voltage 5 for digital parts – Supply voltage 6 for digital parts – Ground for DASL line driver – Ground for USB transceiver – Ground for Analog Front End – Ground for loudspeaker – Ground for LED mux – Ground for PLL – Ground 1 for digital parts – Ground 2 for digital parts – Ground 3 for digital parts – Ground 4 for digital parts – Ground 5 for digital parts – Ground 6 for digital parts 30 2003-03-31 INCA-D PSB 21473 Architectural Overview 3 Architectural Overview 3.1 Functional Block Diagram Block Diagram VREF DSP AMI A/D Dec IOM-2 Interface DIF IBUS DEC CI & TIC XRAM ANALOG FRONTALS END YRAM DSP CORE IOM Transfer Unit HDLC IOM Frame Arbiter PROM UBUS DROM DASLTransceiver Figure 3-1 AXO D/A Int INT UCIF AHO PIDD DPLL OSC X-BUS XRAM 4 K Bytes Boot ROM PMemBUS RAM-BUS External Bus Controller DP-RAM CPU C166 2K Bytes RESET X-BUS SCU PEC EP Info USB POWER ICU PD-BUS (PL) SIE UBL IF PLL (EP0) OCDS KEY SCAN PORT LOGIC P0L Data Sheet P0H Port 4 P1L P1H Port 6 Port 7 31 LEDMUX BPI SSC0 SSC1 GPT ASC JTAG Port 2 Port 3 2003-03-31 INCA-D PSB 21473 Architectural Overview 3.2 Bus Systems The Analog front End and the DSP are connected using dedicated signals which carry the AD converted and precomputed information. The remaining functional units communicate over different busses. The IBUS carries synchronous data corresponding to the IOM-2 interface.It consists of the Bit Clock, a Chip Select signal, a Read/Write strobe signal, a 3 bit address line and 8 bit lines for data in and data out. Unlike the IBUS the UBUS is used to exchange asynchronous data which can be accessed by the CPU core via the UCIF module which connects XBUS and UBUS. The INCA-D provides an on-chip interface (the XBUS interface), which allows to connect integrated customer/application specific peripherals to the standard controller core. The XBUS is an internal representation of the external bus interface, ie. it is operated in the same way. The XBUS provides a full 24-bit address bus and a 16 bit data bus between the CPU and its X-peripherals (the address width of external bus depends on the selected port configuration). On XBUS, one CPU controlled access can be executed every machine cycle. CPU accesses to XBUS peripherals are synchronous processes, which may be delayed by programmable wait states. The differentiation between accesses to external bus or internal XBUS is performed within the bus controller by address range detection. For access to internal XBUS peripherals four different address ranges can be selected, each with its own bus type definition. To each address range belongs a chip select signal which also may be shared between more than one X-peripheral. For accesses to external peripherals 5 address ranges may be selected. The Peripheral (PD) -BUS allows CPU and PEC (Peripheral Event Controller) access to core related and generic peripherals every half machine cycle. The bus cycles are fully synchronized without wait states. The bus also supports read-modify-write cycles without performance losses. Bit modification is provided and bit protection for simultaneous writes is also supported. However, only 512 16-bit registers can be addressed via the demultiplexed address bus. The RAM bus interface provides two 16 bit busses between the dual port RAM and the CPU. Its bus cycles are fully synchronized, with a cycle time of half machine cycle. Thus, four accesses can be made every machine cycle. This performance allows multiple GPR (General Purpose register) accesses to occur without processor stalls. The RAM bus is an internal bus and therefore not visible on core boundary. Data Sheet 32 2003-03-31 INCA-D PSB 21473 Clock Concept 4 Clock Concept The on-chip clock generator provides the INCA-D with all necessary clock signals. Generally, the INCA-D derives its system clocks from an external crystal of 15.36 MHz connected to XTAL1 and XTAL2. An external clock signal may be fed to the input XTAL1, leaving XTAL2 open. The clock signals for the different device modules are generated as described in Figure 4-1. When not disabled by setting bit PPLEN in register CLK_CONF, the on chip PLL generates a signal with a frequency of 96 MHz which is the input signal to a set of fixed and programmable divider. The outputs of the divider are the clock signals for the different device components, which can be disabled separately. Data Sheet 33 2003-03-31 INCA-D PSB 21473 Clock Concept 4.1 Clock Generation The clock generation unit is illustrated in Figure 4-1. DSP (3.84 - 4.17) MHz FAFE FTSF Clock Tracking (:12.5 :12.0 :11.5) 48 MHz D3 Fosc = 15.36 MHz Fosc = 15.36 MHz Fout2 = (48, 38.5 MUX 32, 24, 16) MHz FDSP D2 96 Mhz Fout2= 48 Mhz FUSB AND UCLK enable bit (DCR reg bit 1) 48 Mhz D1 FCPU/Periherals PLL XTAL1 Pad Shaper Oscillator 96 Mhz 15.36 MHz Fout1 MUX Fosc = 15.36 MHz D0 XTAL2 Pad Fout0=Fosc/ (1, 2, 4, 8, 16, 32) FSC DCL Adjust Unit Lla BCL Llb Figure 4-1 Data Sheet Clock Concept 34 2003-03-31 INCA-D PSB 21473 Clock Concept 4.2 Terminal Specific Functions The components realizing the terminal specific functions (Keypad Scanner, LED Multiplex Unit and Pulse Modulation Units) run at a frequency, which is output of divider D3. D3 can not be programmed. The clock signal for the Terminal Specific Functions can not be disabled globally. As described in Chapter 21.3, the different modules can be disabled separately. 4.3 USB For the USB Device Module the necessary clock of 48 MHz is generated using a clock signal which is being generated from the PLL. It’s important to note that the CPU frequency has to be greater or equal than 12 MHz to ensure a proper operation of the USB module. The USB module clock can be disabled by setting bit USB_DIS in the CLK_CONF register to ’1’. Before the USB interface can be used, the USB clock has to be enabled by setting USB_DIS to ’0’ and bit UCLK of the USB Device Control Register DCR has to be set to ’1’ (refer to Chapter 22). A level detect mechanism enables the USB clock as soon as an appropriate level at pins DPLS/DMNS is detected. For further information refer to the USB module description. 4.4 DSP A bypass mechanism allows the DSP to get a clock signal with the oscillator frequency of 15.36 MHz directly. If the bypass is not used, the DSP runs with a PLL generated clock signal at a frequency which can be programmed by setting bitfield DSP_DIV in register CLK_CONF according to Table 4-1. A change of the DSP frequency can only be performed synchronously and glitch free, if the following steps will be applied: • • • • • • Change to the OSC as clock source ( if already running on Oscillator, it’s okay) 5 NOP instructions Change the division factor by programming CLK_CONF.DSP_DIV At least 50 NOP instructions recommended Change the clock source to PLL (if needed) 5 NOP instructions Note: The NOPs are necessary to ensure to have time to change the frequency while the device is running at a much higher frequency as it will be after the change. Data Sheet 35 2003-03-31 INCA-D PSB 21473 Clock Concept The maximum DSP clock frequency of 48 MHz can be reduced, if the full duplex based speakerphone capability is not needed. Without any speakerphone functionality, the lowest frequency of 16 MHz is sufficient for simple phone operation. Generally, the necessary DSP frequency depends on the functional units that are concurrently in use. • Table 4-1 DSP_DIV DSP Frequency Factor Resulting Frequency 000 2.0 48 MHz xx11) 2.5 38.5 MHz 010 3.0 32 MHz 100 4.0 24 MHz 110 6.0 16 MHz 1) x means that either a ’0’ or an ’1’ can be entered 4.5 Microcontroller and Peripherals The peripherals and the CPU are provided with separated clock signals of the same frequency. While the CPU clock is stopped during the idle mode, the peripheral clock keeps running. Both clocks are switched off, when the power down mode is entered. When the powerdown instruction (PWRDWN) is executed, the NMI pin must be low in order to force the CPU to go into power down mode. A bypass mechanism allows to run the CPU without PLL generated signals. In that case divider D0 may be used to control the clocks for CPU and peripherals. The bypass may be controlled by bit CPU_BYP in the CLK_CONF register. After reset, the bypass is active, i.e. the CPU and peripheral frequency will be 7.68 MHz. Afterwards the divider D0 can be modified or PLL generated clock signals can be selected by software. Changing to the PLL clock has to be done only if the bit CLK_CONF.LOCK indicates a stable PLL output clock. The programmable divider D0 and D1 are programmed by setting bitfield OSC_DIV or CPU_DIV respectively of register CLK_CONF to generate the clock fCPU for the CPU and the peripherals. Data Sheet 36 2003-03-31 INCA-D PSB 21473 Clock Concept The factors have to be programmed according to Table 4-2 and Table 4-3. Table 4-2 CPU & Peripheral frequency OSC_DIV Factor D0 Resulting Frequency if PLL is not used 101 1 15.36 MHz 000 2 7.68 MHz 001 4 3.84 MHz 010 8 1.92 MHz 011 16 0.96 MHz 100 32 0.48 MHz 110 reserved reserved 111 Table 4-3 CPU & Peripheral frequency CPU_DIV Factor D1 Resulting Frequency 0000 3 32 MHz 0001 4 24 MHz 0010 6 16 MHz 0011 8 12 MHz 0100 12 8 MHz 0101 16 6 MHz 0110 24 4 MHz 0111 32 3 MHz 1000 48 2 MHz 1001 64 1.5 MHz 1100 96 1.0 MHz A change of the CPU frequency can only be performed synchronously and glitch free, if the following steps will be applied: • Change to the other clock source ( if running on PLL, switch to Oscillator or vice versa) • 5 NOP instructions • Change the division factor by programming CLK_CONF.CPU_DIV or CLK_CONF.OSC_DIV respectively • At least 50 NOP instructions recommended Data Sheet 37 2003-03-31 INCA-D PSB 21473 Clock Concept • Change the clock source back • 5 NOP instructions Note: The NOPs are necessary to ensure to have time to change the frequency while the device is running at a much higher frequency as it will be after the change. The minimum frequency for a proper USB operation is 12 MHz. 4.6 AFE The input clock of the Analog Front End is a 4 MHz clock signal that is generated by a dedicated divider. If enabled (PIDDHWCFG.ACT = 1), the clock tracking unit takes care that the AFE clock is always synchronous to the frame synchronization provided by the interface to the IOM-2 handler. 4.7 IOM-2 clocks The INCA-D operates as clock master and the transmit and receive bit clocks are derived, with the help of the Adjust Unit, from the DASL interface receive data stream. The received signal is sampled several times inside the derived receive clock period, and a majority logic is used to additionally reduce bit error rate in severe conditions. IThe FSC, DCL and BCL clocks are summarized below with the respective duty cycles. FSC 8 kHz 1:2 BCL 768 kHz1:1 DCL 1536 kHz1:1 For further details refer to the IOM-2 handler module description. Data Sheet 38 2003-03-31 INCA-D PSB 21473 Clock Concept 4.8 Register Description of the Clock Concept Unit CLK_CONF (DFAA H) 15 14 CPU DSP _BYP _BYP rw rw 13 - XBUS-SFR 12 11 10 CPU_DIV - 9 - Function PLLEN PLL enable 0: PLL disabled 7 - DSP_DIV rw Bit 8 rw Reset Value: 0000H 6 5 0 LOCK r r 4 3 2 rw 0 USB PLL _DIS EN OSC_DIV rw 1 rw rw rw Note: The PLL should only be disabled after the bypass for the CPU has been enabled, ie. CPU_BYP set to ’0’. Otherwise the behavior is undefined. 1: PLL enabled USB_DIS USB clock disable 0: USB clock enabled 1: USB clock disabled LOCK PLL LOCK 0: PLL not locked; 1: PLL locked, clock source switched to PLL clock if CPU_BYP is ’1’. OSC_DIV CPU Clock Speed Divider value for CPU/Peripheral frequency in bypass mode (refer to Table 4-2) DSP_DIV DSP Clock Speed Divider value for DSP frequency when not in bypass mode (refer to Table 4-1) CPU_DIV CPU Clock Speed Divider value for CPU/Peripheral frequency when not in bypass mode (refer to Table 4-3) DSP_BYP Bypass for DSP Clock 1: PLL generated signal is used; 0: Oscillators generated signal is directly used Note: Because the LOCK bit and the DSP_BYP bit are internally ANDED, the clock source is set to PLL only after the PLL is locked. CPU_BYP Bypass for CPU/Peripheral Clock 1: PLL generated signal is used; 0: Oscillators generated signal is directly used Note: Because the LOCK bit and the CPU_BYP bit are internally ANDED, the clock source is set to PLL only after the PLL is locked. Data Sheet 39 2003-03-31 INCA-D PSB 21473 Memory Organization 5 Memory Organization The memory space of the INCA-D is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal Dual-Port RAM with the internal Special Function Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals and external memory are mapped into one common address space. Generally, the CPU core of the INCA-D provides a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each, and each segment is again subdivided into four data pages of 16 KBytes each However, the addressable external memory space of the INCA-D is limited to 4 MBytes1). Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address. Double words (code only) are stored in ascending memory locations as two subsequent words. Single bits are always stored in the specified bit position at a word address. Bit position 0 is the least significant bit of the byte at an even byte address, and bit position 15 is the most significant bit of the byte at the next odd byte address. Bit addressing is supported for a part of the Special Function Registers, a part of the internal RAM and for the General Purpose Registers. Figure 5-1 1) Storage of Words, Byte and Bits in a Byte Organized Memory Each of the 2 chip selects can be used to access a 4 MB window of memory Data Sheet 40 2003-03-31 INCA-D PSB 21473 Memory Organization Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area. 5.1 Internal ROM (Bootstrap Loader) The INCA-D includes an internal ROM for bootstrap loader functionality only. Therefore, there is no internal ROM available for customized program code storage. The BSL mechanism may be used for standard system startup as well as only for special occasions like system maintenance (firmware update) or end-of-line programming or testing The INCA-D enters BSL mode, if pin P0L.4 is sampled low at the end of a hardware reset (See Chapter 24.6). After entering BSL mode and the respective internal initialization the INCA-D scans the RXD0 line to receive a zero byte, ie. one start bit, eight ‘0’ data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock, initializes the serial interface ASC accordingly and switches pin TxD0 to output. In order to execute a program in normal mode, the BSL mode has to be terminated first. The INCA-D exits BSL mode upon software reset (ignores the level on P0L.4) or a hardware reset (P0L.4 must be high then). After reset the INCA-D will start executing from location 00’0000H of the external memory. 5.2 On Chip XRAM The INCA-D provides 4 KBytes of On Chip XRAM. The XRAM is mapped on data page 3 from address 00’E000H to 00’EFFFH as shown in Figure 5-2. 5.3 Internal Dual-Port-RAM and SFR Area The RAM/SFR area is located within data page 3 and provides access to the internal DPRAM (IRAM, organized as X*16) and to two 512 Byte blocks of Special Function Registers (SFRs). The INCA-D provides 2 KBytes of IRAM, see Figure 5-2. The IRAM serves for several purposes: • • • • • System Stack (programmable size) General Purpose Register Banks (GPRs) Source and destination pointers for the Peripheral Event Controller (PEC) Variable and other data storage, or Code storage. Data Sheet 41 2003-03-31 INCA-D PSB 21473 Memory Organization 5.4 XBUS Peripherals The peripherals can be grouped into peripherals which are connected to the PD-bus (GPT, ASC, SSC) and peripherals which are connected to the XBUS (see Figure 3-1). While the PD-bus peripherals are configured by the SFR or ESFR resprectively, the Xbus peripherals (e.g. USB, I2C, IOM handler) are configured by XBUS SFR’S which are located in the XPER area as described in Figure 5-2. SEGMENT 1 SEGMENT 1 01’0000H IRAM/SFR 00’FFFFH SFR Area 00’FFFFH 00’FE00H XRAM XPER IRAM 2 KByte External Memory 00’F600H Reserved ESFR Area 00’8000H 00’F000H 00’EFFFH XRAM 4 KByte (Boot Program) or External Memory 00’0000H XBUS SFR Area Segment 0 Figure 5-2 00’F200H 00’E000H 00’DFFFH 00’DD00H Memory Areas and Address Space Code accesses are always made on even byte addresses. The highest possible code storage location in the internal DP-RAM is either 00’FDFEH for single word instructions or 00’FDFCH for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results. Any word and byte data in the internal DP-RAM can be accessed via indirect or long 16-bit addressing modes, if the selected DPP register points to data page 3. Data Sheet 42 2003-03-31 INCA-D PSB 21473 Memory Organization Any word data access is made on an even byte address. The highest possible word data storage location in the internal RAM is 00’FDFEH. For PEC data transfers, the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The upper 256 Byte of the internal RAM (00’FD00H through 00’FDFFH) and the GPRs of the current bank are provided for single bit storage, and thus they are bit addressable. 5.5 System Stack The system stack may be defined within the internal DP-RAM. The size of the system stack is controlled by bitfield STKSZ in register SYSCON (see table below). Stack Size (Words) Internal RAM Addresses (Words) 000B 256 00’FBFEH...00’FA00H (Default after Reset) 001B 128 00’FBFEH...00’FB00H 010B 64 00’FBFEH...00’FB80H 011B 32 00’FBFEH...00’FBC0H 100B 512 00’FBFEH...00’F800H 101B --- Reserved. Do not use this combination. 110B --- Reserved. Do not use this combination. 111B 1024 00’FDFEH...00’F600H (Note: No circular stack) For all system stack operations the on-chip DP-RAM is accessed via the Stack Pointer (SP) register. The stack grows downward from higher towards lower RAM address locations. Only word accesses are supported to the system stack. A stack overflow (STKOV) and a stack underflow (STKUN) register are provided to control the lower and upper limits of the selected stack area. These two stack boundary registers can be used not only for protection against data destruction, but also allow to implement a circular stack with hardware supported system stack flushing and filling (except for option ’111’). 5.6 General Purpose Registers The General Purpose Registers (GPRs) use a block of 16 consecutive words within the internal DP-RAM. The Context Pointer (CP) register determines the base address of the currently active register bank. This register bank may consist of up to 16 word GPRs (R0, R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte GPRs are mapped onto the first eight word GPRs (see table below). In contrast to the system stack, a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short 2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address (independent of the current DPP register contents). Data Sheet 43 2003-03-31 INCA-D PSB 21473 Memory Organization Additionally, each bit in the currently active register bank can be accessed individually. Mapping of General Purpose Registers to RAM Addresses Internal RAM Address Byte Registers Word Register + 1EH --- R15 + 1CH --- R14 + 1AH --- R13 + 18H --- R12 + 16H --- R11 + 14H --- R10 + 12H --- R9 + 10H --- R8 + 0EH RH7 RL7 R7 + 0CH RH6 RL6 R6 + 0AH RH5 RL5 R5 + 08H RH4 RL4 R4 + 06H RH3 RL3 R3 + 04H RH2 RL2 R2 + 02H RH1 RL1 R1 + 00H RH0 RL0 R0 The INCA-D supports fast register bank (context) switching. Multiple register banks can physically exist within the internal DP-RAM at the same time. Only the register bank selected by the Context Pointer register (CP) is active at a given time, however. Selecting a new active register bank is simply done by updating the CP register. A particular Switch Context (SCXT) instruction performs register bank switching and an automatic saving of the previous context. The number of implemented register banks (arbitrary sizes) is only limited by the size of the available internal RAM. 5.7 PEC Source and Destination Pointers The 16 word locations in the internal DP-RAM from 00’FCE0H to 00’FCFEH (just below the bit-addressable section) are provided as source and destination address pointers for data transfers using the eight PEC channels. Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer (SRCPx) on the lower and the destination pointer (DSTPx) on the higher word address (x = 7...0). Data Sheet 44 2003-03-31 INCA-D PSB 21473 Memory Organization • 00’FD00 H 00’FCFE H DSTP7 00’FCFE H 00’FCFC H SRCP7 00’FCE0 H 00’FCDE H PEC Source and Destination Pointers Internal RAM 00’FCE2 H DSTP0 00’F600 H 00’FCE0 H SRCP0 00’F5FE H MCD03903 Figure 5-3 Location of the PEC Pointers Whenever a PEC data transfer is performed, the pair of source and destination pointers, which is selected by the specified PEC channel number, is accessed independent of the current DPP register contents and also the locations referred to by these pointers are accessed independent of the current DPP register contents. If a PEC channel is not used, the corresponding pointer location area is available and can be used for word or byte data storage. 5.8 Special Function Registers The functions of the CPU, the bus interface, the I/O ports and the on-chip peripherals of the INCA-D are controlled via a number of so-called Special Function Registers (SFRs). These SFRs are arranged within two areas of 512 Byte size each. The first register block, the SFR area, is located in the 512 Bytes above the internal DP-RAM (00’FFFFH...00’FE00H), the second register block, the Extended SFR (ESFR) area, is located in the 512 Bytes below the internal RAM (00’F1FFH...00’F000H). Special function registers can be addressed via indirect and long 16-bit addressing modes. Using an 8-bit offset together with an implicit base address allows to address word SFRs and their respective low bytes. However, this does not work for the respective high bytes! Data Sheet 45 2003-03-31 INCA-D PSB 21473 Memory Organization Note: Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared! The upper half of each register block is bit-addressable, so the respective control/status bits can directly be modified or checked using bit addressing. 5.9 External Memory Space The INCA-D is capable to address 4 MBytes of external memory space (for each chip select). This external memory is accessed via the INCA-D’s external bus interface. Four memory bank sizes are supported: • • • • Non-segmented mode: 64 KBytes with A15...A0 on PORT0 or PORT1 2-bit segmented mode: 256 KByteswith A17...A16 on Port 4 and A15...A0 on PORT0 or PORT1 4-bit segmented mode: 1 MBytes with A19...A16 on Port 4 and A15...A0 on PORT0 or PORT1 6-bit segmented mode: 4 MBytes with A21...A16 on Port 4 and A15...A0 on PORT0 or PORT1 Each bank can be directly addressed via the address bus, while the programmable chip select signals can be used to select various memory banks. The INCA-D also supports four different bus types: • Multiplexed 16-bit Bus with address and data on PORT0 • Multiplexed 8-bit Bus with address and data on PORT0 or P0L(pins 0-7 of Port0 )respectively • Demultiplexed 16-bit Bus with address on PORT1 and data on PORT0 • Demultiplexed 8-bit Bus with address on PORT1 and data on P0L (Default after Reset) Memory model and bus mode are selected during reset by PORT0 pins. (For further details refer to Chapter ’The External Bus Interface’) Please note that the external memory size of segment 0 is limited to the lower 56 KBytes. If the program code exceeds this boundary, it has to be continued in segment 1. Note: When operating in non-segmented mode only addresses from 00’0000H to 00’CFFFH can be used for external memory access. The different memory areas must be switched explicitly via branch instructions. Sequential boundary crossing is not supported and leads to erroneous results. External word and byte data can only be accessed via indirect or long 16-bit addressing modes using one of the four DPP registers. There is no short addressing mode for external operands. Any word data access is made to an even byte address. For PEC data transfers the external memory can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The external memory is not provided for single bit storage and therefore it is not bit addressable. Data Sheet 46 2003-03-31 INCA-D PSB 21473 Memory Organization 5.10 Crossing Memory Boundaries The address space of the INCA-D is implicitly divided into equally sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these blocks (code or data) or areas requires special attention to ensure that the controller executes the desired operations. Memory Areas are partitions of the address space that represent different kinds of memory (if provided at all). These memory areas are the internal RAM/SFR area, the onchip general purpose RAM and the external memory. Accessing subsequent data locations that belong to different memory areas is no problem. However, when executing code, the different memory areas must be switched explicitly via branch instructions. Sequential boundary crossing is not supported and leads to erroneous results. Segments are contiguous blocks of 64 KByte each. They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme. During code fetching segments are not changed automatically, but rather must be switched explicitly. The instructions JMPS, CALLS and RETS will do this. In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment, to prevent the prefetcher from trying to leave the current segment. Data Pages are contiguous blocks of 16 KByte each. They are referenced via the data page pointers DPP3...0 and via an explicit data page number for data accesses overriding the standard DPP scheme. Each DPP register can select one of the possible 1024 data pages. The DPP register that is used for the current access is selected via the two upper bits of the 16-bit data address. Subsequent 16-bit data addresses that cross the 16 KByte data page boundaries therefore will use different data page pointers, while the physical locations need not be subsequent within memory. Data Sheet 47 2003-03-31 INCA-D PSB 21473 Central Processor Unit 6 Central Processor Unit Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated results. Since a four stage pipeline is implemented in the INCA-D, up to four instructions can be processed in parallel. Most instructions of the INCA-D are executed in one machine cycle (2 CPU clock cycles) due to this parallelism. This chapter describes how the pipeline works for sequential and branch instructions in general, and which hardware provisions have been made to speed the execution of jump instructions in particular. The general instruction timing is described including standard and exceptional timing. While internal memory accesses are normally performed by the CPU itself, external peripheral or memory accesses are performed by a particular on-chip External Bus Controller (EBC), which is automatically invoked by the CPU whenever a code or data address refers to the external address space. If possible, the CPU continues operating while an external memory access is in progress. If external data are required but are not yet available, or if a new external memory access is requested by the CPU, before a previous access has been completed, the CPU will be held by the EBC until the request can be satisfied. The EBC is described in a dedicated chapter. Figure 6-1 Data Sheet CPU Block Diagram 48 2003-03-31 INCA-D PSB 21473 Central Processor Unit The on-chip peripheral units of the INCA-D work nearly independent of the CPU. Data and control information is interchanged between the CPU and these peripherals via Special Function Registers (SFRs). Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them. If the priority of the current CPU operation is lower than the priority of the selected peripheral request, an interrupt will occur. A set of Special Function Registers is dedicated to the functions of the CPU core: •General System Configuration: SYSCON (RP0H) •CPU Status Indication and Control: PSW •Code Access Control: IP, CSP •Data Paging Control: DPP0, DPP1, DPP2, DPP3 •GPRs Access Control: CP •System Stack Access Control: SP, STKUN, STKOV •Multiply and Divide Support: MDL, MDH, MDC •ALU Constants Support: ZEROS, ONES 6.1 Instruction Pipelining The instruction pipeline of the INCA-D partitiones instruction processing into four stages of which each one has its individual task: 1st –>FETCH: In this stage the instruction selected by the Instruction Pointer (IP) and the Code Segment Pointer (CSP) is fetched from either the internal ROM (bootstrap loader), internal RAM, or external memory. 2nd –>DECODE: In this stage the instructions are decoded and, if required, the operand addresses are calculated and the respective operands are fetched. For all instructions, which implicitly access the system stack, the SP register is either decremented or incremented, as specified. For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address (provided that the branch is taken). 3rd –>EXECUTE: In this stage an operation is performed on the previously fetched operands in the ALU. Additionally, the condition flags in the PSW register are updated as specified by the instruction. All explicit writes to the SFR memory space and all auto-increment or autodecrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction, too. Data Sheet 49 2003-03-31 INCA-D PSB 21473 Central Processor Unit 4th –>WRITE BACK: In this stage all external operands and the remaining operands within the internal RAM space are written back. A particularity of the INCA-D are the so-called injected instructions. These injected instructions are generated internally by the machine to provide the time needed to process instructions, which cannot be processed within one machine cycle. They are automatically injected into the decode stage of the pipeline, and then they pass through the remaining stages like every standard instruction. Program interrupts are performed by means of injected instructions, too. Although these internally injected instructions will not be noticed in reality, they are introduced here to ease the explanation of the pipeline in the following. Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not. Since passing through one pipeline stage takes at least one machine cycle, any isolated instruction takes at least four machine cycles to be completed. Pipelining, however, allows parallel (ie. simultaneous) processing of up to four instructions. Thus, most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset (see figure below). Instruction pipelining increases the average instruction throughput considered over a certain period of time. In the following, any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing. 1 Machine Cycle FETCH I1 DECODE EXECUTE I2 I3 I4 I5 I6 I1 I2 I3 I4 I5 I1 I2 I3 I4 I1 I2 I3 WRITEBACK time Figure 6-2 Data Sheet Sequential Instruction PipeliningI 50 2003-03-31 INCA-D PSB 21473 Central Processor Unit 6.2 CPU Special Function Registers The core CPU requires a set of Special Function Registers (SFRs) to maintain the system state information, to supply the ALU with register-addressable constants and to control system and bus configuration, multiply and divide ALU operations, code memory segmentation, data memory paging, and accesses to the General Purpose Registers and the System Stack. The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR. Since all SFRs can simply be controlled by means of any instruction, which is capable of addressing the SFR memory space, a lot of flexibility has been gained, without the need to create a set of system-specific instructions. Note, however, that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations. The instruction pointer IP and code segment pointer CSP cannot be accessed directly at all. They can only be changed indirectly via branch instructions. The PSW, SP, and MDC registers can be modified not only explicitly by the programmer, but also implicitly by the CPU during normal instruction processing. Note that any explicit write request (via software) to an SFR supersedes a simultaneous modification by hardware of the same register. Note: Any write operation to a single byte of an SFR clears the non-addressed complementary byte within the specified SFR. Non-implemented (reserved) SFR bits cannot be modified, and will always supply a read value of '0'. Data Sheet 51 2003-03-31 INCA-D PSB 21473 Central Processor Unit The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset . SYSCON (FF12H / 89H) 15 14 13 STKSZ rw SFR-b 12 11 10 9 0 SGT DIS 0 BYT DIS r rw r rw 8 7 Reset Value: EA84H 6 CLK WR CS EN CFG CFG rw rw rw 5 4 3 0 0 0 r r r 2 1 0 VISI 0 rw r XPEN BLE rw Bit Function VISIBLE Visible Mode Control 0: Accesses to XBUS peripherals are done internally 1: XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0: Accesses to the on-chip X-Peripherals and their functions are disabled 1: The on-chip X-Peripherals are enabled and can be accessed CSCFG Chip Select Configuration Control 0: Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins synchronously. 1: Unlatched CS mode. The CS signals are directly derived from the address and driven to the (enabled) port pins. WRCFG Write Configuration Control (Set according to pin P0H.0 during reset) 0: Pins WR and BHE retain their normal function 1: Pin WR acts as WRL, pin BHE acts as WRH CLKEN System Clock Output Enable (CLKOUT 1)) 0: 1: CLKOUT disabled CLKOUT enabled; BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width) 0: Pin BHE enabled 1: Pin BHE disabled, pin may be used for general purpose I/O SGTDIS Segmentation Disable/Enable Control ‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit) ‘1’: Segmentation disabled (Only IP is saved/restored) STKSZ System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words 1) The implemented pad type for CLKOUT supports only an open-drain output driver Note: Register SYSCON cannot be changed after execution of the EINIT instruction. Data Sheet 52 2003-03-31 INCA-D PSB 21473 Central Processor Unit Note: Only exception: bit VISIBLE can also be changed by the on-chip debug support with DPEC access. System Clock Output Enable (CLKEN) The system clock output function is enabled by setting bit CLKEN in register SYSCON to '1'. If enabled, port pin P3.15 takes on its alternate function as CLKOUT output pin. The clock output is a 50 % duty cycle clock whose frequency equals the CPU operating frequency (fOUT = fCPU). Note: The output driver of port pin P3.15 is switched on automatically, when the CLKOUT function is enabled. The port direction bit is disgarded. After reset, the clock output function is disabled (CLKEN = ‘0’). Note: The implemented pad type for CLKOUT supports only an open-drain output driver Segmentation Disable/Enable Control (SGTDIS) Bit SGTDIS allows to select either the segmented or non-segmented memory mode. In non-segmented memory mode (SGTDIS='1') it is assumed that the code address space is restricted to 64 KBytes (segment 0) and thus 16 bits are sufficient to represent all code addresses. For implicit stack operations (CALL or RET) the CSP register is totally ignored and only the IP is saved to and restored from the stack. In segmented memory mode (SGTDIS='0') it is assumed that the whole address space is available for instructions. For implicit stack operations (CALL or RET) the CSP register and the IP are saved to and restored from the stack. After reset the segmented memory mode is selected. Note: Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered, and it is repopped when the interrupt service routine is left again. System Stack Size (STKSZ) This bitfield defines the size of the physical system stack, which is located in the internal RAM of the INCA-D. An area of 32...1024 words may be dedicated to the system stack. A so-called “circular stack” mechanism allows to use a bigger virtual stack than this dedicated RAM area. The Processor Status Word PSW This bit-addressable register reflects the current state of the microcontroller. Two groups of bits represent the current ALU status, and the current CPU interrupt status. A separate bit (USR0) within register PSW is provided as a general purpose user flag. Data Sheet 53 2003-03-31 INCA-D PSB 21473 Central Processor Unit PSW (FF10H / 88H) 15 14 13 ILVL rw 12 SFR 11 10 9 IEN 0 0 rw r r 8 0 7 0 r r Reset Value: 0000H 6 0 5 4 MUL E IP 3 Z 2 V 1 C 0 N r rw rw rw rw rw rw Bit Function N Negative Result Set, when the result of an ALU operation is negative. C Carry Flag Set, when the result of an ALU operation produces a carry bit. V Overflow Result Set, when the result of an ALU operation produces an overflow. Z Zero Flag Set, when the result of an ALU operation is zero. E End of Table Flag Set, when the source operand of an instruction is 8000H or 80H. MULIP Multiplication/Division In Progress ‘0’: There is no multiplication/division in progress. ‘1’: A multiplication/division has been interrupted. ILVL, IEN Interrupt and EBC Control Fields Define the response to interrupt requests and enable external bus arbitration. (Described in section “Interrupt and Trap Functions”) • ALU Status (N, C, V, Z, E, MULIP) The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status due to the last recently performed ALU operation. They are set by most of the instructions due to specific rules, which depend on the ALU or data movement operation performed by an instruction. After execution of an instruction which explicitly updates the PSW register, the condition flags cannot be interpreted as described in the following, because any explicit write to the PSW register supersedes the condition flag values, which are implicitly generated by the CPU. Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction. Note: After reset, all of the ALU status bits are cleared. • N-Flag: For most of the ALU operations, the N-flag is set to '1', if the most significant bit of the result contains a '1', otherwise it is cleared. In the case of integer operations the N-flag can be interpreted as the sign bit of the result (negative: N=’1’, positive: N=’0’). Negative numbers are always represented as the 2's complement of the corresponding Data Sheet 54 2003-03-31 INCA-D PSB 21473 Central Processor Unit positive number. The range of signed numbers extends from '–8000H' to '+7FFFH' for the word data type, or from '–80H' to '+7FH' for the byte data type.For Boolean bit operations with only one operand the N-flag represents the previous state of the specified bit. For Boolean bit operations with two operands the N-flag represents the logical XORing of the two specified bits. • C-Flag: After an addition the C-flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated. After a subtraction or a comparison the C-flag indicates a borrow, which represents the logical negation of a carry for the addition. This means that the C-flag is set to '1', if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction, which is performed internally by the ALU as a 2's complement addition, and the C-flag is cleared when this complement addition caused a carry. The C-flag is always cleared for logical, multiply and divide ALU operations, because these operations cannot cause a carry anyhow. For shift and rotate operations the C-flag represents the value of the bit shifted out last. If a shift count of zero is specified, the C-flag will be cleared. The C-flag is also cleared for a prioritize ALU operation, because a '1' is never shifted out of the MSB during the normalization of an operand. For Boolean bit operations with only one operand the C-flag is always cleared. For Boolean bit operations with two operands the C-flag represents the logical ANDing of the two specified bits. • V-Flag: For addition, subtraction and 2's complementation the V-flag is always set to '1', if the result overflows the maximum range of signed numbers, which are representable by either 16 bits for word operations ('–8000H' to '+7FFFH'), or by 8 bits for byte operations ('–80H' to '+7FH'), otherwise the V-flag is cleared. Note that the result of an integer addition, integer subtraction, or 2's complement is not valid, if the V-flag indicates an arithmetic overflow. For multiplication and division the V-flag is set to '1', if the result cannot be represented in a word data type, otherwise it is cleared. Note that a division by zero will always cause an overflow. In contrast to the result of a division, the result of a multiplication is valid regardless of whether the V-flag is set to '1' or not. Since logical ALU operations cannot produce an invalid result, the V-flag is cleared by these operations. The V-flag is also used as 'Sticky Bit' for rotate right and shift right operations. With only using the C-flag, a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result. In conjunction with the V-flag, the C-flag allows evaluating the rounding error with a finer resolution (see table below). For Boolean bit operations with only one operand the V-flag is always cleared. For Data Sheet 55 2003-03-31 INCA-D PSB 21473 Central Processor Unit Boolean bit operations with two operands the V-flag represents the logical ORing of the two specified bits. Table 6-1 Shift Right Rounding Error Evaluation C-Flag V-Flag Rounding Error Quantity 0 0 1 1 0 1 0 1 0< No rounding error Rounding error Rounding error Rounding error < 1/2 LSB = 1/2 LSB > 1/2 LSB • Z-Flag: The Z-flag is normally set to '1', if the result of an ALU operation equals zero, otherwise it is cleared. For the addition and subtraction with carry the Z-flag is only set to '1', if the Z-flag already contains a '1' and the result of the current ALU operation additionally equals zero. This mechanism is provided for the support of multiple precision calculations. For Boolean bit operations with only one operand the Z-flag represents the logical negation of the previous state of the specified bit. For Boolean bit operations with two operands the Z-flag represents the logical NORing of the two specified bits. For the prioritize ALU operation the Z-flag indicates, if the second operand was zero or not. • E-Flag: The E-flag can be altered by instructions, which perform ALU or data movement operations. The E-flag is cleared by those instructions which cannot be reasonably used for table search operations. In all other cases the E-flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not. If the value of the source operand of an instruction equals the lowest negative number, which is representable by the data format of the corresponding instruction ('8000H' for the word data type, or '80H' for the byte data type), the E-flag is set to '1', otherwise it is cleared. • MULIP-Flag: The MULIP-flag will be set to '1' by hardware upon the entrance into an interrupt service routine, when a multiply or divide ALU operation was interrupted before completion. Depending on the state of the MULIP bit, the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service. The MULIP bit is overwritten with the contents of the stacked MULIP-flag when the return-from-interrupt-instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again after that. Note: The MULIP flag is a part of the task environment! When the interrupting service routine does not return to the interrupted multiply/divide instruction (ie. in case of a task scheduler that switches between independent tasks), the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered. Data Sheet 56 2003-03-31 INCA-D PSB 21473 Central Processor Unit CPU Interrupt Status (IEN, ILVL) The Interrupt Enable bit allows to globally enable (IEN=’1’) or disable (IEN=’0’) interrupts. The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level is updated by hardware upon entry into an interrupt service routine, but it can also be modified via software to prevent other interrupts from being acknowledged. In case an interrupt level '15' has been assigned to the CPU, it has the highest possible priority, and thus the current CPU operation cannot be interrupted except by hardware traps or external non-maskable interrupts. For details please refer to chapter “Interrupt and Trap Functions”. After reset all interrupts are globally disabled, and the lowest priority (ILVL=0) is assigned to the initial CPU activity. The Instruction Pointer IP This register determines the 16-bit intra-segment address of the currently fetched instruction within the code segment selected by the CSP register. The IP register is not mapped into the INCA-D's address space, and thus it is not directly accessable by the programmer. The IP can, however, be modified indirectly via the stack by means of a return instruction. The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations. IP (---- / --) 15 14 --- 13 12 11 10 9 8 7 Reset Value: 0000H 6 5 4 3 2 1 0 ip rw Bit Function ip Specifies the intra segment offset, from where the current instruction is to be fetched. IP refers to the current segment . The Code Segment Pointer CSP This non-bit addressable register selects the code segment being used at run-time to access instructions. The lower 8 bits of register CSP select one of up to 256 segments of 64 KBytes each, while the upper 8 bits are reserved for future use. Data Sheet 57 2003-03-31 INCA-D PSB 21473 Central Processor Unit CSP (FE08H / 04H) SFR 15 14 13 12 11 10 9 8 - - - - - - - - 7 Reset Value: 0000H 6 5 4 3 2 SEGNR 1 0 r Bit Function SEGNR Segment Number Specifies the code segment, from where the current instruction is to be fetched. SEGNR is ignored, when segmentation is disabled. Code memory addresses are generated by directly extending the 16-bit contents of the IP register by the contents of the CSP register as shown in the figure below. In the case of the segmented memory mode, the selected number of segment address bits (via bitfield SALSEL) of register CSP is output on the respective segment address pins of Port 4 for all external code accesses. For non-segmented memory mode, the content of this register is not significant, because all code acccesses are automatically restricted to segment 0. Note: The CSP register can only be read but not written by data operations. It is, however, modified either directly by means of the JMPS and CALLS instructions, or indirectly via the stack by means of the RETS and RETI instructions. Upon the acceptance of an interrupt or the execution of a software TRAP instruction, the CSP register is automatically set to zero. Data Sheet 58 2003-03-31 INCA-D PSB 21473 Central Processor Unit • Figure 6-3 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address. The Data Page Pointers DPP0, DPP1, DPP2, DPP3 These four non-bit addressable registers select up to four different data pages being active simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024 possible 16-Kbyte data pages while the upper 6 bits are reserved for future use. The DPP registers allow to access the entire memory space in pages of 16 Kbytes each. The DPP registers are implicitly used, whenever data accesses to any memory location are made via indirect or direct long 16-bit addressing modes (except for override accesses via EXTended instructions and PEC data transfers). After reset, the Data Page Pointers are initialized in a way that all indirect or direct long 16-bit addresses result in identical 18-bit addresses. This allows to access data pages 3...0 within segment 0 as shown in the figure below. If the user does not want to use any data paging, no further action is required. Data Sheet 59 2003-03-31 INCA-D PSB 21473 Central Processor Unit DPP0 (FE00H / 00H) SFR 15 14 13 12 11 10 - - - - - - 9 8 7 Reset Value: 0000H 6 5 4 3 DPP0PN SFR 14 13 12 11 10 - - - - - - 9 8 7 Reset Value: 0001H 6 5 4 3 DPP1PN SFR 14 13 12 11 10 - - - - - - 9 8 13 12 11 10 - - - - - - 1 0 7 Reset Value: 0002H 6 5 4 3 DPP2PN SFR 14 2 2 1 0 rw DPP3 (FE06H / 03H) 15 0 rw DPP2 (FE04H / 02H) 15 1 rw DPP1 (FE02H / 01H) 15 2 9 8 7 Reset Value: 0003H 6 5 4 3 DPP3PN 2 1 0 rw Bit Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx. Only the least significant two bits of DPPx are significant, when segmentation is disabled. Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16-bit address with the contents of the DPP register selected by the upper two bits of the 16-bit address. The content of the selected DPP register specifies one of the 1024 possible data pages. This data page base address together with the 14-bit page offset forms the physical 24-bit address (selectable part is driven to the address pins). In case of non-segmented memory mode, only the two least significant bits of the implicitly selected DPP register are used to generate the physical address. Thus, extreme care should be taken when changing the content of a DPP register, if a nonsegmented memory model is selected, because otherwise unexpected results could occur. Data Sheet 60 2003-03-31 INCA-D PSB 21473 Central Processor Unit In case of the segmented memory mode the selected number of segment address bits (via bitfield SALSEL) of the respective DPP register is output on the respective segment address pins of Port 4 for all external data accesses. A DPP register can be updated via any instruction, which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register. After reset or with segmentation disabled the DPP registers select data pages 3...0. All of the internal memory is accessible in these cases. Figure 6-4 Addressing via the Data Page Pointers The Context Pointer CP This non-bit addressable register is used to select the current register context. This means that the CP register value determines the address of the first General Purpose Register (GPR) within the current register bank of up to 16 wordwide and/or bytewide GPRs. Data Sheet 61 2003-03-31 INCA-D PSB 21473 Central Processor Unit CP (FE10H / 08H) SFR 15 1 14 1 13 1 12 1 r r r r 11 10 9 8 7 Reset Value: FC00H 6 cp rw 5 4 3 2 1 0 0 r Bit Function cp Modifiable portion of register CP Specifies the (word) base address of the current register bank. When writing a value to register CP with bits CP.11...CP.9 = ‘000’, bits CP.11...CP.10 are set to ‘11’ by hardware, in all other cases all bits of bit field “cp” receive the written value. Note: It is the user's responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location. If this condition is not met, unexpected results may occur. • Do not set CP below the IRAM start address, ie. 00’F600H • Do not set CP above 00’FDFEH • Be careful using the upper GPRs with CP above 00’FDE0H The CP register can be updated via any instruction which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register. The Switch Context instruction (SCXT) allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle. Data Sheet 62 2003-03-31 INCA-D PSB 21473 Central Processor Unit • Figure 6-5 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations. The addressing modes mentioned below are described in chapter “Instruction Set Summary”. Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the memory location specified by the contents of the CP register, ie. the base of the current register bank. Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the short 4-bit GPR address is either multiplied by two or not before it is added to the content of register CP (see figure below). Thus, both byte and word GPR accesses are possible in this way. GPRs used as indirect address pointers are always accessed wordwise. For some instructions only the first four GPRs can be used as indirect address pointers. These GPRs are specified via short 2-bit GPR addresses. The respective physical address calculation is identical to that for the short 4-bit GPR addresses. Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0H to FFH interpret the four least significant bits as short 4-bit GPR address, while the four most significant bits are ignored. The respective physical GPR address calculation is identical to that for the short 4-bit GPR addresses. Data Sheet 63 2003-03-31 INCA-D PSB 21473 Central Processor Unit For single bit accesses on a GPR, the GPR's word address is calculated as just described, but the position of the bit within the word is specified by a separate additional 4-bit value. Figure 6-6 Implicit CP Use by Short GPR Addressing Modes The Stack Pointer SP This non-bit addressable register is used to point to the top of the internal system stack (TOS). The SP register is pre-decremented whenever data is to be pushed onto the stack, and it is post-incremented whenever data is to be popped from the stack. Thus, the system stack grows from higher toward lower memory locations. Since the least significant bit of register SP is tied to '0' and bits 15 through 12 are tied to '1' by hardware, the SP register can only contain values from F000H to FFFEH. This allows to access a physical stack within the internal RAM of the INCA-D. A virtual stack (usually bigger) can be realized via software. This mechanism is supported by registers STKOV and STKUN (see respective descriptions below). The SP register can be updated via any instruction, which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a POP or RETURN instruction must not immediately follow an instruction updating the SP register. SP (FE12H / 09H) SFR 15 1 14 1 13 1 12 1 r r r r Data Sheet 11 10 9 8 7 Reset Value: FC00H 6 sp rw 64 5 4 3 2 1 0 0 r 2003-03-31 INCA-D PSB 21473 Central Processor Unit Bit Function sp Modifiable portion of register SP Specifies the top of the internal system stack. The Stack Overflow Pointer STKOV This non-bit addressable register is compared against the SP register after each operation, which pushes data onto the system stack (eg. PUSH and CALL instructions or interrupts) and after each subtraction from the SP register. If the content of the SP register is less than the content of the STKOV register, a stack overflow hardware trap will occur. Since the least significant bit of register STKOV is tied to '0' and bits 15 through 12 are tied to '1' by hardware, the STKOV register can only contain values from F000H to FFFEH. STKOV (FE14H / 0AH) 15 1 14 1 13 1 12 1 r r r r SFR 11 10 9 8 7 Reset Value: FA00H 6 5 stkov 4 rw Bit Function stkov Modifiable portion of register STKOV Specifies the lower limit of the internal system stack. 3 2 1 0 0 r The Stack Overflow Trap (entered when (SP) < (STKOV)) may be used in two different ways: • Fatal error indication treats the stack overflow as a system error through the associated trap service routine. Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap. • Automatic system stack flushing allows to use the system stack as a 'Stack Cache' for a bigger external user stack. In this case register STKOV should be initialized to a value, which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size. This considers the worst case that will occur, when a stack overflow condition is detected just during entry into an interrupt service routine. Then, six additional stack word locations are required to push IP, PSW, and CSP for both the interrupt service routine and the hardware trap service routine. More details about the stack overflow trap service routine and virtual stack management are given in chapter “System Programming”. Data Sheet 65 2003-03-31 INCA-D PSB 21473 Central Processor Unit The Stack Underflow Pointer STKUN This non-bit addressable register is compared against the SP register after each operation, which pops data from the system stack (eg. POP and RET instructions) and after each addition to the SP register. If the content of the SP register is greater than the the content of the STKUN register, a stack underflow hardware trap will occur. Since the least significant bit of register STKUN is tied to '0' and bits 15 through 12 are tied to '1' by hardware, the STKUN register can only contain values from F000H to FFFEH. STKUN (FE16H / 0BH) 15 1 14 1 13 1 12 1 r r r r SFR 11 10 9 8 7 Reset Value: FC00H 6 5 stkun 4 3 2 1 rw Bit Function stkun Modifiable portion of register STKUN Specifies the upper limit of the internal system stack. 0 0 r The Stack Underflow Trap (entered when (SP) > (STKUN)) may be used in two different ways: • Fatal error indication treats the stack underflow as a system error through the associated trap service routine. • Automatic system stack refilling allows to use the system stack as a 'Stack Cache' for a bigger external user stack. In this case register STKUN should be initialized to a value, which represents the desired highest Bottom of Stack address. More details about the stack underflow trap service routine and virtual stack management are given in chapter “System Programming”. Scope of Stack Limit Control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations (explicit or implicit, ie. CALL or RET instructions). This control mechanism is not triggered, ie. no stack trap is generated, when • the stack pointer SP is directly updated via MOV instructions • the limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the new limits. Data Sheet 66 2003-03-31 INCA-D PSB 21473 Central Processor Unit The Multiply/Divide High Register MDH This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the high order 16 bits of the 32-bit result. For long divisions, the MDH register must be loaded with the high order 16 bits of the 32-bit dividend before the division is started. After any division, register MDH represents the 16-bit remainder. MDH (FE0CH / 06H) 15 14 13 12 SFR 11 10 9 8 7 mdh Reset Value: 0000H 6 5 4 3 2 1 0 rw Bit Function mdh Specifies the high order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, register MDH must be saved along with registers MDL and MDC to avoid erroneous results. A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in chapter “System Programming”. The Multiply/Divide Low Register MDL This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the low order 16 bits of the 32-bit result. For long divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the division is started. After any division, register MDL represents the 16bit quotient. MDL (FE0EH / 07H) 15 14 13 12 SFR 11 10 9 8 7 mdl Reset Value: 0000H 6 5 4 3 2 1 0 rw Data Sheet 67 2003-03-31 INCA-D PSB 21473 Central Processor Unit Bit Function mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. The MDRIU flag is cleared, whenever the MDL register is read via software. When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, register MDL must be saved along with registers MDH and MDC to avoid erroneous results. A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in chapter “System Programming”. Data Sheet 68 2003-03-31 INCA-D PSB 21473 Central Processor Unit The Multiply/Divide Control Register MDC This bit addressable 16-bit register is implicitly used by the CPU, when it performs a multiplication or a division. It is used to store the required control information for the corresponding multiply or divide operation. Register MDC is updated by hardware during each single cycle of a multiply or divide instruction. MDC (FF0EH / 87H) SFR Reset Value: 0000H 15 14 13 12 11 10 9 8 7 !! 6 !! 5 4 3 !! MDR !! IU 2 !! 1 !! 0 !! - - - - - - - - rw) rw) rw) rw) rw) rw) rw) rw) Bit Function MDRIU Multiply/Divide Register In Use ‘0’: Cleared, when register MDL is read via software. ‘1’: Set when register MDL or MDH is written via software, or when a multiply or divide instruction is executed. !! Internal Machine Status The multiply/divide unit uses these bits to control internal operations. Never modify these bits without saving and restoring register MDC. When a division or multiplication was interrupted before its completion and the multiply/ divide unit is required, the MDC register must first be saved along with registers MDH and MDL (to be able to restart the interrupted operation later), and then it must be cleared prepare it for the new calculation. After completion of the new division or multiplication, the state of the interrupted multiply or divide operation must be restored. The MDRIU flag is the only portion of the MDC register which might be of interest for the user. The remaining portions of the MDC register are reserved for dedicated use by the hardware, and should never be modified by the user in another way than described above. Otherwise, a correct continuation of an interrupted multiply or divide operation cannot be guaranteed. A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in chapter “System Programming”. The Constant Zeros Register ZEROS All bits of this bit-addressable register are fixed to '0' by hardware. This register can be read only. Register ZEROS can be used as a register-addressable constant of all zeros, ie. for bit manipulation or mask generation. It can be accessed via any instruction, which is capable of addressing an SFR. Data Sheet 69 2003-03-31 INCA-D PSB 21473 Central Processor Unit ZEROS (FF1CH / 8EH) SFR Reset Value: 0000H 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 r r r r r r r r r r r r r r r r The Constant Ones Register ONES All bits of this bit-addressable register are fixed to '1' by hardware. This register can be read only. Register ONES can be used as a register-addressable constant of all ones, ie. for bit manipulation or mask generation. It can be accessed via any instruction, which is capable of addressing an SFR. ONES (FF1EH / 8FH) SFR Reset Value: FFFFH 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 r r r r r r r r r r r r r r r r 6.3 PEC - Extension of Functionality Introduction Compared to existing C16x architecture, the PEC transfer function is enhanced by extended functionality. For information regarding the general PEC transfer refer to the interrupt description. However, the extended PEC function is a further step into DMA control functionality. It especially supports integrated system design with XBUS as system bus. The extended PEC functions are defined as follows: – Source pointer and destination pointer are extended to 24-bit pointer, thus enabling PEC controlled data transfer between any two locations within the total address space. Both 8-bit segment numbers of every source/destination pointer pair are defined in one 16-bit SFR register; thus, 8 PEC segment number registers are available for the 8 PEC channels. – Two of the PEC channels are expanded by additional 16-bit transfer count registers; when enabled, the original 8-bit bytecount in the control register serves as package length count, thus defining the amount of bytes or words to be transferred with one request. In INCA-D the package size is always limited to one transfer. – For always two channels a chaining feature is provided. When enabled in the PEC control register, a termination interrupt of one channel will automatically switch transfer control to the other channel of the channel pair. Data Sheet 70 2003-03-31 INCA-D PSB 21473 Central Processor Unit 24-bit Extension of Source and Destination Pointers The source and destination pointers specify the locations between which the data is to be moved. For each of the eight PEC channels the source and destination pointers are specified by one SFR register and two IRAM memory locations. One SFR register stores the 8-bit segment number of the source (PECSSN) and the 8-bit segment number of the destination (PECDSN) location in a respective 16-bit PEC Segment Number register (PECSNx). The respective segment offset of source and destination are stored in IRAM memory location identical to the IRAM locations of SRCPx and DSTPx pointers of FullCustom C16x standard PEC channels - thus the extension is fully compatible. With the segment number extension of source and destination, data can be transferred by a PEC transfer between any two locations within the 16 MByte address space of the INCA-D. Note: The segment number extension of source and destination is provided for all 8 PEC channels. After reset, all 8 segment number registers PECSNx are cleared, providing full compatibility to FC-C16x PEC channels. Data Sheet 71 2003-03-31 INCA-D PSB 21473 Central Processor Unit The PEC segment number registers PECSNx are defined as follows: PECSNx (Addresses see table) 15 14 13 SFR 12 11 10 PECDSN 9 8 7 Reset Value: 0000H 6 5 4 3 2 PECSSN rw 1 0 rw Bit Function PECSSN PEC Source Segment Number 8-bit Segment Number (address bits A23-A16) used for addressing the source of the respective PEC transfer. PECDSN PEC Destination Segment Number 8-bit Segment Number (address bits A23-A16) used for addressing the destination of the respective PEC transfer. Table 6-2 PEC Segment Number Register Addresses Register Address Reg. Space Register Address Reg. Space PECSN0 FED0H / 68H SFR PECSN4 FED8H / 6CH SFR PECSN1 FED2H / 69H SFR PECSN5 FEDAH / 6DH SFR PECSN2 FED4H / 6AH SFR PECSN6 FEDCH / 6EH SFR PECSN3 FED6H / 6BH SFR PECSN7 FEDEH / 6FH SFR Data Sheet 72 2003-03-31 INCA-D PSB 21473 Central Processor Unit Extended PEC Channel Control The PEC control registers with the extended functionality and their application for new PEC control are defined as follows: PECCx (Addresses: see table) SFR 15 14 13 12 11 PT - - CLT CL INC BWT COUNT rw - - rw rw rw rw rw PECXC0/1 15 14 - - 10 9 (Addresses: see table) 8 Reset Value: 0000H 7 6 5 SFR 4 3 - - - 1 0 Reset Value: 0000H 3 - 2 2 1 0 COUNT2 rw Bit Function COUNT PEC Transfer Count Counts PEC transfers (bytes or words) and influences the channel’s action BWT Byte / Word Transfer Selection 0: Transfer a Word 1: Transfer a Byte INC Increment Control (Modification of SRCPx or DSTPx) 0 0: Pointers are not modified 0 1: Increment DSTPx by 1 or 2 (BWT) 1 0: Increment SRCPx by 1 or 2 (BWT) 1 1: Reserved. Do not use this combination. (changed to 10 by hardware) CL Channel Link Control 0: PEC channels work independent 1: Pairs of channels are linked together CLT Channel Link Toggle State 0: Even numbered PEC channel of linked channels active 1: Odd numbered PEC channel of linked channels active PT Package Transfer 0: Single Transfer; extended Count2 not enabled 1: Package Transfer; extended Count2 enabled (only for channels 1 and 2) Note : Package Transfer is only supported in PECC2 and PECC0 Bit Function COUNT2 PEC Extended Transfer Count PEC transfer count extension (see table below) Data Sheet 73 2003-03-31 INCA-D PSB 21473 Central Processor Unit Table 6-3 PEC Control Register Addresses Register Address Reg. Space Register Address Reg. Space PECC0 FEC0H / 60H SFR PECC4 FEC8H / 64H SFR PECC1 FEC2H / 61H SFR PECC5 FECAH / 65H SFR PECC2 FEC4H / 62H SFR PECC6 FECCH / 66H SFR PECC3 FEC6H / 63H SFR PECC7 FECEH / 67H SFR PECXC0 FEF0H/78H SFR PECXC1 FEF2H/79H SFR Long Transfer Count with Package Transfer The features of the C16x PEC functions are expanded by long transfer counts and package transfers, where a package is a container with always the same defined number of bytes or words. If enabled by the PT flag in PECCx, each service request initiates an entire package of data to be transferred by the PEC channel. The length of data packages is determined by the PEC Transfer COUNT in the PECCx register, the amount of package transfers is defined by the long 16-bit transfer count COUNT2 in the new PECXCx register. In PT mode, packages of up to 256 bytes or words are supported. The PEC transfer COUNT2 allows to service up to 64K transfer requests by the respective PEC channel, and then (when COUNT2 reaches 00H) activate the interrupt service routine in the CPU as known from standard PEC channels. After each PEC package transfer the COUNT2 field is decremented by one and the request flag is cleared to indicate that the request has been serviced. Note: Within a package transfer only every second machine cycle is a PEC transfer cycle. Note: In INCA-D, the package length is limited to 1 transfer (COUNT field must be 01H). Therefore only the long transfer count COUNT2 which enables block lengths of up to 64K transfers, is available in Package Transfer mode (the PT flag is set in PECCx register). Package transfers with COUNT>1 are not supported. Note: The PT mode is available for two PEC channels: PECC2 and PECC0. These two channels with long transfer counts can also be used in Channel Link Mode (see below), to be concatenated with channel 3 and channel 1. Data Sheet 74 2003-03-31 INCA-D PSB 21473 Central Processor Unit Channel Link Mode for Data Chaining Data chaining with linked PEC channels is enabled, if the Channel Link Control Bit in PECCx register is set to ’1’, either in one or both PEC channel control registers of a channel pair. In this case, two PEC channels are linked together and handle chained block transfers alternatively to each other. The whole data transfer is divided into several block transfers where each block is controlled by one PEC channel of a channel pair. When a data block is completely transferred a channel link interrupt is generated and the PEC service request processing is automatically switched to the ’other’ PEC channel of the channel-pair. Thus, PEC service requests addressed to a linked PEC channel are either handled by linked PEC channel A or by linked PEC channel B. This channel toggle allows to set up shadow and multiple buffers for PEC transfers by changing pointer and count values of one channel while the other channel is active. The following table list the channels that can be linked together and the channel numbers to address the linked channels. Table 6-4 PEC Channels which could be linked together Linked PEC Channels Linked PEC Channel PEC Channel A PEC Channel B channel 0 channel 1 channel 0 channel 2 channel 3 channel 2 channel 4 channel 5 channel 4 channel 6 channel 7 channel 6 For each pair of linked channels, an internal channel flag, the Channel Link Toggle flag CLT identifies which of the two PEC channels will serve the next PEC request. The CLT flag is indicated in both PECCx registers of two linked PEC channels, where the CLT bit in channel B always is inverse to the CLT bit in channel A. The very first transfer is always started with the channel A if the CLT bit was not programmed otherwise before. The CLT bit is only valid in case of linked PEC channels, indicated by the CL bits of linked channels. If linking is not enabled, the CLT bit of both channels is always zero (compatibility!). The internal channel link flag CLT toggles, and the other channel begins service with the next request if the "old" channel stops the service (COUNT=0 or COUNT2=0, dependent on the mode), and if the new channel has in its PEC control register the CL flag enabled and its transfer count is more than zero. Note: With the last transfer of a block transfer (COUNT=0 or COUNT2=0), the channel link control flag CL of that channel is cleared in its PECCx register. If the channel link flag CL of the new (chained) PEC control register is found to be zero the whole data transfer is finished and the channel link interrupt is coincidently a termination interrupt. Data Sheet 75 2003-03-31 INCA-D PSB 21473 Central Processor Unit The channel link mode is finished and the internal channel toggle flag is cleared after the last transfer of the block, if the CL flags of both pair channels are cleared. Additional Interrupt Request Node for Channel Link Interrupts The PEC Unit has one dedicated service request node (trap number) for all channel link interrupts. This service request node requests CPU interrupt service in case of one or more channel link request flag and the respective enable control bit is set in the channel link interrupt subnode control register (CLISNC). These flags indicate a channel link interrupt condition of linked PEC channels (A and B channels) which requires support by the CPU. The following channel link interrupt conditions requesting CPU service are possible: – In single transfer mode a COUNT value change from 01H to 00H in a linked PEC channel and CL flag is set in the respective PEC control register. – In package transfer mode a COUNT2 value change from 0001H to 0000H in a linked PEC channel and CL flag is set in the belonging PEC control register. In these cases the CPU service is requested to update the PEC control and pointer registers while the next block transfer is executed (the whole transfer is divided into separately controlled block transfers). The last block transfer is determined by the missing link bit in the new (linked) PEC control register. If a new service request hits a linked channel with count equal to zero and channel link flag disabled, a standard interrupt is performed as known from standard PEC channels. The channel link interrupt subnode register CLISNC is defined as follows: CLISNC (FFA8H / D4H) 15 14 13 12 - - C6 IR C6 IE - - rw rw SFR-b 11 10 9 8 - - C4 IR C4 IE - - rw rw 7 Reset Value: 0000H 6 5 4 - - C2 IR C2 IE - - rw rw 3 2 1 0 - - C0 IR C0 IE - - rw rw Bit Function xxIE PEC Channel Link Interrupt Enable Control Bit (individually enables/disables a specific channel pair interrupt request) ‘0’: PEC interrupt request is disabled ‘1’: PEC interrupt request is enabled xxIR PEC Channel Service Request Flag ‘0’: No channel link service request pending ‘1’: This source (channel pair) has raised an request to service a PEC channel after channel linking Data Sheet 76 2003-03-31 INCA-D PSB 21473 Central Processor Unit 6.4 XBUS System Architecture 6.4.1 Bus Access Control CPU accesses to internal and external busses, thus internal or external memories or peripherals are controlled with the respective address ranges. These address ranges are supported for on-chip XBUS resources or for external off-chip resources. In INCA-D four address ranges with according bus definitions must be programmed for on-chip XBUS peripherals (including memories) . Address ranges and thus address mappings of peripherals, which communicate over the internal XBUS are controlled by address selection registers XADRSx. The respective bus type definitions are controlled with registers XBCONx. Generally, the definition for the XADRSx and XBCONx registers is very similar to the defintion of the registers of the External Bus Interface. The XADRSx registers and XBCONx registers are defined as follows: F014H (F016H)(F018H) (F01AH) XADRS1(2)(3)(4) 15 14 13 12 11 10 9 8 7 ESFR 6 5 Reset Value: 0000H 4 3 RGSAD 2 1 RGSZ rw rw Range Size RGSZ Selected Address Range Relvant(R) bits of RGSAD Selected Range Start Address (Relevant(R) bits of RGSAD) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx 256 Byte 512 Bytes 1 KBytes 2 KBytes 4 KBytes 8 KBytes 16 KBytes 32 KBytes 64 KBytes 128 KBytes 256 KBytes 512 KBytes - reserved RRRR RRRR RRRR RRRR RRRR RRRR RRRR RRRR RRRR RRR0 RR00 R000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Data Sheet RRRR RRRR RRRR RRRR RRRR RRR0 RR00 R000 0000 0000 0000 0000 0 RRRR RRR0 RR00 R000 0000 0000 0000 0000 0000 0000 0000 0000 77 RRRR RRRR RRRR RRRR RRRR RRRR RRRR RRRR RRRR RRR0 RR00 R000 RRRR RRRR RRRR RRRR RRRR RRR0 RR00 R000 0000 0000 0000 0000 RRRR RRR0 RR00 R000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2003-03-31 INCA-D PSB 21473 Central Processor Unit Table 6-5 Address Range and Address Range Start Definition of XADRSx register Bit Function RGSAD Address Range Start Address Selection RGSZ Address Range Size Selection F114H (F116H)(F118H)(F11AH) XBCON1(2)(3)(4) 15 14 13 - - - - - - 12 11 10 9 8 7 RDY BS BUS ALE EW ENx WCx ACTx CTLx ENx rw rw rw rw rw ESFR-b 6 Reset Value: 0000H 5 4 3 2 1 BTYPx MT TCx RW DCx MCTCx rw rw rw rw 0 Bit Function MCTCx Memory Cycle Time Control 0 0 0 0 : 15 waitstates (Number = 15 - ) ... 1 1 1 1 : No waitstates RWDCx READ/WRITE Delay Control ‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE ‘1’: No read/write delay: activate command with falling edge of ALE MTTCx Memory Tri-state Time Control ‘0’: 1 waitstate ‘1’: No waitstate BTYPx Bus Type Selection; only demultiplexed busses are supported on XBUS; ’00’: 8 bit bus ’10’: 16 bit bus; ’x1’: reserved. EWENx Early Write Enable ’0’: Standard write enable signal control ’1’: Write active state is disabled one TCL earlier ALECTLx ALE Lengthening Control Bit (see BUSCON) BUSACTx Bus Active Control ‘0’: XBUS (peripheral) disabled ‘1’: XBUS (peripheral) enabled Enables the XBUS and the according chip select XCSx for the respective address window (respective XBUS peripheral), selected with according XADRSx window; after reset, all address windows on XBUS are disabled. Data Sheet 78 2003-03-31 INCA-D PSB 21473 Central Processor Unit Bit Function BSWCx BUSCON Switch Control ’0’: Standard switch of bustype (switch of XBCON) ’1’: A bus wait state (Tri-state cycle) is included after execution of last oldbustype cycle and before the first new-bustype cycle after switch of XBCON or BUSCON; the BSWC bit is indicated in the old-bustype XBCON/BUSCON. RDYENx READY Enable ’0’: The bus cycle length is controlled by the bus controller using MCTC ’1’: The bus cycle length is controlled by the peripheral using READY The smallest possible adress range, which is covered with respect to the XADRSx register, is 256 bytes. For a better utilization of that memory , the address ranges are in two cases shared by some XBUS peripherals as described in the table below. After reset, no address selection register is selected; thus the default address range is enabled and controlled with BUSCON0 and additionally the chip select output CS0 is activated (as in standard C16x architecture). In order to use the on-chip XBUS peripherals , the XADRSx and XBCONx registers must be programmed in a certain way. The XBUS peripherals correspond to the register pairs XADRSx and XBCONx as follows: Table 6-6 XBUS peripherals groups Group number corresonding peripherals registers 1 PIDD, TSF, I2C XBCON1 & XADRS1 2 IOM handler, HDLC controller, Transceiver, CI Handler XBCON2 & XADRS2 3 USB XBCON3 & XADRS3 4 XRAM XBCON4 & XADRS4 All XADRSx/ADDRSELx registers as well as XBCONx/BUSCONx registers are user programmable SFR registers. All BUSCONx registers are mapped into the bitaddressable SFR memory space, all XBCONx registers are located in the bitaddressable ESFR memory space. Although they are free programmable, programming should be performed during the initialisation phase before the first accesses are controlled with XBCONx or BUSCONx. Wait states of IOM2 block Since the IOM2 block contains modules which have wide variations in their uC access times, wait states assignment for the different blocks is dynamic. To implement this dynamic wait state assignment scheme the IOM2 access by the uC is implemented by Data Sheet 79 2003-03-31 INCA-D PSB 21473 Central Processor Unit using synchronous handshaking (via the READY signal). The assertion of the READY signal by the IOM2 is based on the values programmed in the IOM2 Wait States Register (IWSR). Without wait states a single c166 access takes 2 XCLK cycles. Hence with a wait state of 2, the access will last 4 XCLK cycles. Thus the waitstates for the IOM-2 handler block are not controlled by the XBCON2 register, but by the dedicated IOM-waitstate register IWSR. Please refer to Chapter 17.6.6.7 for further information. Wait state for accesses to the USB block Because the memory management unit of the USB module needs 3 clock cycles for an read access to the setup token memory, but a CPU access to the XBUS takes 2 CPU cycles (= 1 machine cycle), one 1 wait state has to be programmed to read the setup token. (compare XBCON3 programming in Table 6-7 ) In order to ensure correct access of the on-chip XBUS peripheral groups, the registers XADRSx must be set to the values shown in table 6-7 prior to the use of the corresponding peripherals. See also Figure 25-1. Table 6-7 ADRSx and XBCONx values to be programmed (E)SFR Value XADRS1 0DF0H XADRS2 0DE0H XADRS3 0DD0H XADRS4 0E04H XBCON1 04BFH XBCON2 1437H XBCON3 043FH 043EH ( for setup token read only (for details refer to Chapter 22) XBCON4 04BFH 6.4.2 XBUS Peripheral Configuration Block Because of compatibility (to C16x) the XBUS peripheral groups can be separately selected for being visible by means of corresponding selection bits in the XPERCON register. If not selected and therefore not enabled (not activated with XPERCON bit), the peripheral’s address space including SFR addresses and port pins are not occupied by the peripheral, thus the peripheral is not visible and not available. Data Sheet 80 2003-03-31 INCA-D PSB 21473 Central Processor Unit XPERCON (F024H / 12H) 15 14 13 12 11 ESFR 10 9 8 7 Reset Value : 0000H 6 5 4 3 2 1 XPER XPER XPER XPER 4 3 2 1 Reserved 0 R Bit Field Bits Type Value Description XPER1 1 rw 0 1 PIDD, IIC and TSF modules are not visible PIDD, IIC and TSF modules are selected and visible XPER2 1 rw 0 IOM handler, CI handler, HDLC controller and line transceiver are not visible IOM handler, CI handler, HDLC controller and line transceiver are selected and visible 1 XPER3 1 rw 0 1 USB interface is not visible USB interface is selected and visible XPER4 1 rw 0 1 XRAM is not visible XRAM is selected and visible XPERx remaining bits R = Reserved To make an XBUS peripheral group visible, its related bit in XPERCON register must be set before the XPERs are globally enabled with XPEN-bit in SYSCON register (during system initialization be fore EINIT instruction). After reset, no XBUS peripheral is selected in XPERCON register. Data Sheet 81 2003-03-31 INCA-D PSB 21473 Integrated OCDS Support 7 Integrated OCDS Support On Chip Debug Support (OCDS) is implemented to provide the most important hardware emulation features without special emulation chips at minimum cost. Note: For more detailed information please refer to ’OCDS C166CBC Target Specification V.1.5’ Features of OCDS: • Hardware, software and external pin breakpoints (BRKIN, BRKOUT) • Up to 4 instruction pointer breakpoints • Masked comparisons for hardware breakpoints • Independent modules for OCDS and debug port (interface to external debugger) • The OCDS can also be configured by a monitor • Trace support in conjunction with the debug port • Support of multi CPU systems • Single stepping with monitor or CPU halt Basically, debug operations are controlled with debug events and event actions: • Debug events: • Hardware trigger combination • Execution of a DEBUG instruction • Break pin input • Debug event actions: • Halt the CPU • Call a monitor • Trigger a data transfer (DPEC) • Activate external pin 7.1 Applications of OCDS The application of OCDS is to debug the user software running on the CPU in the customer’s system. This is done with an external debugger, that controls the OCDS via the independent debug port. An standard (IEEE 1149.1) JTAG interface can be used as independent port to the OCDS within C166CBC systems. Via the JTAG interface and the integrateds modulle called Cerberus, the external debug hardware can access the OCDS registers and arbitrary memory locations with the new DPEC mechanism. DPEC transfers are PEC transfers, executed by the core CPU, but controlled by the Cerberus. With DPEC transfers, injected into the CPU’s pipeline or executed in CPU-Hold state, data exchange can be executed by the Cerberus module within the whole address space, including all SFRs and dual-port RAM as well as program or data Flash modules on chip (for example). Data Sheet 82 2003-03-31 INCA-D PSB 21473 Integrated OCDS Support Features of Cerberus: • Generic serial link to address the whole user address space • External host controls all transactions • JTAG interface is used as control and data channel • Generic memory read/write functionality (RW mode) • Full support for communication between monitor and external debugger (communication mode) • Optional error protection • Pending reads (writes) can be optional triggered from the OCDS module (low end tracing) PD Bus X Bus OCDS C166CBC External DPEC Debugger Cerberus C166CBC Figure 7-1 Data Sheet JTAG Module Block Diagram of Cerberus/OCDS integration 83 2003-03-31 INCA-D PSB 21473 Interrupts 8 Interrupts The architecture of the INCA-D supports several mechanisms for fast and flexible response to service requests that can be generated from various sources. These mechanisms include: Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an interrupt service routine in order to service an interrupt requesting device. The current program status (IP, PSW, in segmentation mode also CSP) is saved on the internal system stack. A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled. Interrupt Processing via the Peripheral Event Controller (PEC) A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the INCA-D's integrated Peripheral Event Controller (PEC). Triggered by an interrupt request, the PEC performs a single word or byte data transfer between any two locations in the whole memory space through one of eight programmable PEC Service Channels. During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle. No internal program status information needs to be saved. The same prioritization scheme is used for PEC service as for normal interrupt processing. PEC transfers share the 2 highest priority levels. Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions. A trap can also be caused externally by the Non-Maskable Interrupt pin NMI. Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction. Hardware traps always have highest priority and cause immediate system reaction. The software trap function is invoked by the TRAP instruction, which generates a software interrupt for a specified interrupt vector. For all types of traps the current program status is saved on the system stack. External Interrupt Processing The INCA-D allows to connect external interrupt sources and provides several mechanisms to react on external events, including standard inputs, non-maskable interrupts and fast external interrupts. Data Sheet 84 2003-03-31 INCA-D PSB 21473 Interrupts 8.1 Interrupt System Structure The INCA-D provides up to 27 separate interrupt nodes that may be assigned to 16 priority levels. Each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector. The control register contains the interrupt request flag, the interrupt enable bit, and the interrupt priority of the associated source. The INCA-D provides a vectored interrupt system. In this system specific vector locations in the memory space are reserved for the reset, trap, and interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated with the respective interrupt source. This allows direct identification of the source that caused the request. The only exceptions are the class B hardware traps, which all share the same interrupt vector. The status flags in the Trap Flag Register (TFR) can then be used to determine which exception caused the trap. For the special software TRAP instruction, the vector address is specified by the operand field of the instruction, which is a seven bit trap number. The reserved vector locations build a jump table in the low end of the INCA-D’s address space (segment 0). The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines, which may be located anywhere within the address space. Each jump table entry occupies 2 words, except for the reset vector and the hardware trap vectors, which occupy 4 or 8 words. The table below lists all sources that are capable of requesting interrupt or PEC service in the INCA-D, the associated interrupt vectors, their locations, their trap numbers and the SFR addresses of associated interrupt control registers. It also lists the mnemonics of the corresponding Interrupt Enable flags. The mnemonics are composed of a part that specifies the respective source, followed by a part that specifies their function (IE=Interrupt Enable flag). The same composition is used for the mnemonics of according interrupt request flags (IR=Interrupt Request flag; example: CC0IR belongs to interrupt source CC0INT) and for the names of according interrupt control registers (IC=Interrupt Control; example: CC0IC) which are not included in Table 8-1. Table 8-1 INCA-D Interrupts and PEC Service Requests Nr. Source of Interrupt Interrupt Name or PEC Service Request Enable Flag Vector Trap SFR Location Number Adr. irq(0) GPT Timer 2 T2INT T2IE 00’005CH 17H / 23D FF86 irq(1) GPT Timer 3 T3INT T3IE 00’0084H 21H / 33D FF9E irq(2) USB Endpoint 1 USBEP1INT USBEP1IE 00’0080H 20H / 32D FF9C irq(3) USB Device Interrupts USBINT USBIE 00’00A4H 29H / 41D FF9A Data Sheet 85 2003-03-31 INCA-D PSB 21473 Interrupts Nr. Source of Interrupt Interrupt or PEC Service Name Request Enable Flag Vector Trap SFR Location Number Adr. irq(4) USB Endpoint 0 USB Endpoint 5-15 USBEPINT USBEPIE 00’00A0H 28H / 40D FF98 irq(5) IOM Data Transfer Unit IOMTRA1INT IOM1IE 00’0058H 16H /22D FF84 irq(6) IOM Data Transfer Unit IOMTRA2INT IOM2IE 00’0054H 15H / 21D FF82 irq(7) IOM Data Transfer Unit IOMTRA3INT IOM3IE 00’0050H 14H / 20D FF80 irq(8) IOM Data Transfer Unit IOMTRA4INT IOM4IE 00’004CH 13H / 19D FF7E irq(9) IOM Data Transfer Unit IOMTRA5INT IOM5IE 00’0088H 22H / 34D FF60 irq(10) IOM Data Transfer Unit IOMTRA6INT IOM6IE 00’008CH 23H / 35D FF62 irq(11) IOM Data Transfer Unit IOMTRA7INT IOM7IE 00’0090H 24H / 36D FF64 irq(12) IOM Data Transfer Unit IOMTRA8INT IOM8IE 00’0094H 25H / 37D FF66 irq(13) IOM Handler Keyscanner Parallel Interface to DSP COMB1INT COMB1IE 00’0098H 26H / 38D FF68 irq(14) Software 0-2 COMB2INT Ext. Interrupt 3-7 ASC, SSC, GPT4-6, CAPREL COMB2IE 00’00A8H 2AH / 42D FF6C irq(15) ASC Transmit Buffer S0TBIR S0TBIE 00’011CH 47H / 71D F19C irq(16) ASC Receive S0RIR S0RIE 00’00ACH 2BH / 43D FF6E irq(17) USB Endpoint 3 USBEP3INT USBEP3IE 00’00B0H 2CH / 44D FF70 irq(18) SSC Receive SSCRINT SSCRIE 00’00B8H 2EH /46D FF74 irq(19) I2C Data Transmision Event ICINTE ICINTEIE 00’0118H 46H / 70D F194 irq(20) USB Endpoint 2 USBEP2INT USBEP2IE 00’00BCH 2FH / 47D FF76 Data Sheet 86 2003-03-31 INCA-D PSB 21473 Interrupts Nr. Source of Interrupt Interrupt or PEC Service Name Request Enable Flag Vector Trap SFR Location Number Adr. irq(21) USB Endpoint 4 USBEP4INT USBEP4IE 00’0040H 10H / 16D FF78 irq(22) I2C Data Transfer Event Interrupt IICINTDINT IICINTDIE 00’009CH 27H / 39D FF6A irq(23) SSC Transmit SSCTINT SSCTIE 00’00B4H 2DH /45D FF72 irq(24) Fast Ext. Interrupt FEX0INT FEX0IE 00’0060H 18H / 24D FF88 irq(25) Fast Ext. Interrupt FEX1INT FEX1IE 00’0064H 19H / 25D FF8A irq(26) Fast Ext. Interrupt FEX2INT FEX2IE 00’0068H 1AH / 26D FF8C Note: Each entry of the interrupt vector table provides space for two word instructions or one doubleword instruction. The respective vector location results from multiplying the trap number by 4 (4 bytes per entry). Per interrupt node one Interrupt Control register is provided. The names of Interrupt Control registers are composed of a part that specifies the interrupt source followed by two letters that specify the function of register. Table 8-2 lists the vector locations for hardware traps and the corresponding status flags in register TFR. It also lists the priorities of trap service for cases, where more than one trap condition might be detected within the same instruction. After any reset (hardware reset, software reset instruction SRST, or reset by watchdog timer overflow) program execution starts at the reset vector at location 00’0000H. Reset conditions have priority over every other system activity and therefore have the highest priority (trap priority III). Software traps may be initiated to any vector location between 00’0000H and 00’01FCH. A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW. This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests. Data Sheet 87 2003-03-31 INCA-D PSB 21473 Interrupts • Table 8-2 Hardware Traps and Vector Locations Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority RESET RESET RESET 00’0000H 00’0000H 00’0000H 00H 00H 00H III III III NMI STKOF STKUF DEBUG NMITRAP STOTRAP STUTRAP DEBTRAP 00’0008H 00’0010H 00’0018H 00’0020H 02H 04H 06H 08H II II II II UNDOPC PRTFLT # ILLOPA BTRAP BTRAP 00’0028H 00’0028H 0AH 0AH I I BTRAP 00’0028H 0AH I ILLINA ILLBUS BTRAP BTRAP 00’0028H 00’0028H 0AH 0AH I I Reserved [2CH – 3CH] [0BH – 0FH] Software Traps TRAP Instruction Any [00’0000H – 00’01FCH] in steps of 4H Any [00H – 7FH] Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Debug Trap Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Current CPU Priority Note: A software reset is also executed in case of not allowed instruction access to the memory. Data Sheet 88 2003-03-31 INCA-D PSB 21473 Interrupts 8.2 Combined Interrupt Sources Some events in the INCA-D are indicated by means of a single interrupt output. Thus the interrupt request nodes irq(3), irq(4), irq(13) and irq(14) represent combined interrupt requests. Since only one interrupt line is provided, the cause of an interrupt can be determined by reading the corresponding interrupt node status registers which belongs to the interrupt node. These nodes are described in the following sub-chapters. The name of status register referring to node irq(x) is IRQxx_STA. Note: After reading the interrupt request or interrupt status register, they will be cleared. 8.2.1 Interrupt Node 3 (USBINT) The interrupt 3 comprises all interrupts that are related to the USB device itself. The USB device interrupt request register DIRR contains the device specific interrupt flags of the USB module. These flags are set after the occurrence of special events. If a request flag has been set, it is automatically cleared after a read operation of the DIRR register. The interrupts contained in the DIRR register can individually be masked in the DIER register. For further details refer to Chapter 22. The structure is shown in figure 8-1. Data Sheet 89 2003-03-31 INCA-D PSB 21473 Interrupts • Device Interrupts SE0I DIRR.7 SE0IE DIER.7 DAI DIRR.6 DAIE DIER.6 DDI DIRR.5 DDIE DIER.5 SBI DIRR.4 SBIE >1 DIER.4 USBINT SEI DIRR.3 SEIE DIER.3 STI DIRR.2 STIE DIER.2 SUI DIRR.1 SUIE DIER.1 SOFI DIRR.0 SOFIE DIER.0 DRVI CIARI.0 DRVIE CIARIE.0 Request flag is cleared by hardware after the corresponding register has been read Figure 8-1 Combined interrupts for USBINT Additionally, the Configuration, Interface and Alternate Setting Interrupt request Register (CIARI) sends an interrupt to the uC whenever the host programs multiple device configurations or interfaces. Data Sheet 90 2003-03-31 INCA-D PSB 21473 Interrupts 8.2.2 Interrupt Node 4 (USBEPINT) The interrupt node 4 handles all interrupts that are related to the USB endpoints EP0 and EP5-EP15. The different interrupt sources are handled by the EPIEn (Endpoint Interrupt Enable Register for Endpoint n), EPIRn ((Endpoint Interrupt Request Register for Endpoint n) and EPBCn register (Endpoint n Buffer Control Registerfor Endpoint n) of the USB module. For further details refer to Chapter 22. Endpoint Interrupts Endpoint 15 Interrupts Endpoint 14 Interrupts ... ... Endpoint ... 7 Interrupts Endpoint 6 Interrupts Endpoint 5 Interrupts Endpoint 0 Interrupts ACK0 EPIR0.7 AIE0 EPIE0.7 >1 NACK0 EPIR0.6 NAIE0 GEPIE0 EPIE0.6 EPBC0.4 RLE0 EPIR0.5 USBEPINT RLEIE0 EPIE0.5 >1 DNR0 EPIR0.3 DNRIE0 EPI0 GEPIR.0 EPIE0.3 NOD0 EPIR0.2 NODIE0 EPIE0.2 EOD0 EPIR0.1 EODIE0 EPIE0.1 SOD0 EPIR0.0 SODIE0 EPIE0.7 Request flag is cleared by hardware after the corresponding register has been read Figure 8-2 Data Sheet Combined interrupts for USBEPINT 91 2003-03-31 INCA-D PSB 21473 Interrupts 8.2.3 Interrupt Node 13 (COMB1INT) The interrupts of the Keypad scanner, the PIDD (parallel interface to the DSP), IOM-2 Handler, HDLC controller and the Line transceiver are combined to interrupt node COMB1INT, which belongs to interrupt node 13. The status register IRQ13_STA contains the interrupt request bits of the different interrupt sources. The mask register IRQ13_MSK can be used to selectively mask interrupts of the different sources. The corrresponding registers are described in the dedicated chapters. Table 8-3 Combined Interrupt Sources of node 13 Interrupt Sources Bit in Status Register Source of Interrupt Keypad Scanner KEYIR no further collection Parallel Interface to DSP PIDDIR IOM Transfer Unit ITRFRIR no further collection no further collection HDLC controller HDLCIR RME HDLC controller HDLCIR RPF HDLC controller HDLCIR RFO HDLC controller HDLCIR XPR HDLC controller HDLCIR XMR HDLC controller HDLCIR XDU Transceiver Level Detect TRANIR LD Transceiver Info changed TRANIR RIC CI Handler CICIR CIC0 CI Handler CICIR CIC1 Synchronous Transfer Unit STIR STIxy Synchronous Transfer Unit STIR STOVxy Data Sheet 92 2003-03-31 INCA-D PSB 21473 Interrupts IRQ13_STA IRQ13_MSK STIR CICIR ITRFRIE ITRFRIR PIDDIE PIDDIR TRANIE TRANIR KEYIE KEYIR HDLCIE HDLCIR Figure 8-3 Data Sheet ASTI ACK21 ACK20 ACK11 ACK10 IOM handler Transfer Unit CIC0 CIC1 CIR0 CI1E CIX1 MASKTR LD RIC TIC/CI handler RME RPF RFO XPR RME RPF RFO XPR XMR XDU XMR XDU MASKH ISTAH ISTATR LD RIC HDLC Controller COMB1INT STI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 Transceiver STIE CICIE MSTI STOV21 STOV20 STOV11 STOV10 STI21 STI20 STI11 STI10 Combined Interrupts of node 13 93 2003-03-31 INCA-D PSB 21473 Interrupts I IRQ13_STA (DF20)H XBUS-SFR Reset Value:0000H •H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 - - - - - - - - 7 6 5 4 3 2 1 0 HDLCIR KEYIR ITRFRIR CICIR STIR 0 rw rw rw rw rw - TRANIR PIDDIR rw rw Bit Value Meaning STIR, CICIR ITRFRIR PIDDIR TRANIR KEYIR HDLCIR 0 no INT request originating from corresponding registers (compare with Figure 8-3) STIR, CICIR ITRFRIR PIDDIR TRANIR KEYIR HDLCIR 1 INT request from corresponding registers Data Sheet 94 2003-03-31 INCA-D PSB 21473 Interrupts IRQ13_MSK (DF22H) XBUS-SFR Reset Value: 0000H 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 - - - - - - - - 7 6 5 4 3 2 1 0 HDLCI KEYI TRANI PIDDI ITRFRI CICI STI 0 rw rw rw rw rw rw rw - Bit Value Meaning STI , CICI 0 ITRFRI PIDDI TRANI KEYI HDLCI Interrupt request of the dedicated source is not masked (compare with Figure 8-3) STI , CICI 1 ITRFRI PIDDI TRANI KEYI HDLCI Interrupt request of the dedicated source is masked (compare with Figure 8-3) Data Sheet 95 2003-03-31 INCA-D PSB 21473 Interrupts 8.2.4 Interrupt Node 14 (COMB2INT) Different interrupt sources are combined to interrupt COMB2INT as listed in Table 8-4. This interrupt belongs to interrupt node 14. The status register IRQ14_STA contains the interrupt request bits of the different interrupt sources. The mask register IRQ14_MSK can be used to selectively mask interrupts of the different sources. Table 8-4 Combined Interrupt Sources of Node 14 Interrupt Sources Bit in Status Register GPT Timer 4 T4IR GPT Timer 5 T5IR GPT Timer 6 T6IR GPT2 CAPREL CRIR Software Interrupt 0 SW0IR Software Interrupt 1 SW1IR Software Interrupt 2 SW2IR ASC transmit S0TIR ASC error S0EIR SSC error SSCEIR I2C Protocol Event ICINTPIR External Interrupt 3 E3IR External Interrupt 4 E4IR External Interrupt 5 E5IR External Interrupt 6 E6IR Externall Interrupt 7 E7IR Data Sheet 96 2003-03-31 INCA-D PSB 21473 Interrupts IRQ14_STA (DF24H) XBUS-SFR Reset Value: 0000H • 15 14 13 12 11 10 9 E7IR E6IR E5IR E4IR E3IR rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 S0TIR SW2IR SW1IR SW0IR CRIR T6IR T5IR T4IR rw rw rw rw rw rw rw rw ICINTPIR SSCEIR Bit Value Meaning (all) 0 no INT request originating from corresponding source (compare with Table 8-4) 1 INT request from corresponding source IRQ14_MSK (DF26H) XBUS-SFR 8 S0EIR Reset Value: 0000H • 15 14 13 12 11 10 9 8 E7I E6I E5I E4I E3I ICINTPI SSCEI S0EI rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 S0TI SW2I SW1I SW0I CRI T6I T5I T4I rw rw rw rw rw rw rw rw Bit Value Meaning (all) 0 interrupt requests from the corresponding sources are not masked (compare with Table 8-4) 1 INT from corresponding source is masked Data Sheet 97 2003-03-31 INCA-D PSB 21473 Interrupts COMB2INT Figure 8-4 8.2.5 IRQ14_MSK IRQ14_STA T4I T4IR T5I T5IR T6I T6IR CRI CRIR SW0I SW0IR SW1I SW1IR SW2I SW2IR S0TI TIR S0EI EIR SSCEI SSCEIR ICINTPI ICINTPIR E3I E4I E5I E3IR E4IR E5IR EX5INT E6I E7I E6IR E7IR Combined Interrupts of node 14 Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority. This priority of interrupts and PEC requests is programmable in two levels. Each requesting source can be assigned to a specific priority. A second level (called “group priority”) allows to specify an internal order for simultaneous requests from a group of different sources on the same priority level. At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system. This request will then be serviced, if its priority is higher than the current CPU priority in register PSW. 8.2.6 Interrupt System Register Description Interrupt processing is controlled globally by register PSW through a general interrupt enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt sources are controlled individually by their specific interrupt control registers (...IC). Thus, the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW. PEC services are controlled by the respective PECCx register and the source and destination pointers, which specify the task of the respective PEC service channel. Data Sheet 98 2003-03-31 INCA-D PSB 21473 Interrupts 8.3 Interrupt Control Registers All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source, which is required during one round of prioritization, the upper 8 bits of the respective register are reserved. All interrupt control registers are bit-addressable and all bits can be read or written via software. This allows each interrupt source to be programmed or modified with just one instruction. When accessing interrupt control registers through instructions which operate on word data types, their upper 8 bits (15...8) will return zeros, when read, and will discard written data. The layout of the Interrupt Control registers shown below applies to each xxIC register, where xx stands for the mnemonic for the respective source. xxIC (yyyyH / XXH) SFR Reset Value: xxxx xxxx 0000 0000 •H 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 xxIR xxIE ILVL GLVL rw rw rw rw Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. FH: Highest priority level 0H: Lowest priority level Data Sheet 99 2003-03-31 INCA-D PSB 21473 Interrupts xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) ‘0’: Interrupt request is disabled ‘1’: Interrupt Request is enabled xxIR Interrupt Request Flag ‘0’: No request pending ‘1’: This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs. It is cleared automatically upon entry into the interrupt service routine or upon a PEC service. In the case of PEC service the Interrupt Request flag remains set, if the COUNT field in register PECCx of the selected PEC channel decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC block transfer. Note: Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware. Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests. The priority increases with the numerical value of ILVL, so 0000B is the lowest and 1111B is the highest priority level. When more than one interrupt request on a specific level gets active at the same time, the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced. Again the group priority increases with the numerical value of GLVL, so 00B is the lowest and 11B is the highest group priority. Note: All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities. Otherwise an incorrect interrupt vector will be generated. Upon entry into the interrupt service routine, the priority level of the source that won the arbitration and who’s priority level is higher than the current CPU level, is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack. The interrupt system of the INCA-D allows nesting of up to 15 interrupt service routines of different priority levels (level 0 cannot be arbitrated). Interrupt requests that are programmed to priority levels 15 or 14 (ie, ILVL=111XB) will be serviced by the PEC, unless the COUNT field of the associated PECC register contains zero. In this case the request will instead be serviced by normal interrupt processing. Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing. Data Sheet 100 2003-03-31 INCA-D PSB 21473 Interrupts Note: Priority level 0000B is the default level of the CPU. Therefore a request on level 0 will never be serviced, because it can never interrupt the CPU. However, an enabled interrupt request on level 0000B will terminate the INCA-D’s Idle mode and reactivate the CPU. For interrupt requests which are to be serviced by the PEC, the associated PEC channel number is derived from the respective ILVL (LSB) and GLVL (see figure below). So programming a source to priority level 15 (ILVL=1111B) selects the PEC channel group 7...4, programming a source to priority level 14 (ILVL=1110B) selects the PEC channel group 3...0. The actual PEC channel number is then determined by the group priority field GLVL. Interrupt Control Register PEC Control Figure 8-5 Priority Levels and PEC Channels Simultaneous requests for PEC channels are prioritized according to the PEC channel number, where channel 0 has lowest and channel 7 has highest priority. Note: All sources that request PEC service must be programmed to different PEC channels. Otherwise an incorrect PEC channel may be activated. The table below shows in a few examples, which action is executed with a given programming of an interrupt control register. • Priority Level Type of Service COUNT = 00H COUNT ≠ 00H 1111 11 CPU interrupt, level 15, group priority 3 PEC service, channel 7 1111 10 CPU interrupt, level 15, group priority 2 PEC service, channel 6 1110 10 CPU interrupt, level 14, group priority 2 PEC service, channel 2 1101 10 CPU interrupt, level 13, group priority 2 CPU interrupt, level 13, group priority 2 ILVL GLVL Data Sheet 101 2003-03-31 INCA-D PSB 21473 Interrupts Priority Level Type of Service COUNT = 00H COUNT ≠ 00H 0001 11 CPU interrupt, level 1, group priority 3 CPU interrupt, level 1, group priority 3 0001 00 CPU interrupt, level 1, group priority 0 CPU interrupt, level 1, group priority 0 0000 XX No service! No service! ILVL GLVL Note: All requests on levels 13...1 cannot initiate PEC transfers. They are always serviced by an interrupt service routine. No PECC register is associated and no COUNT field is checked. Interrupt Control Functions in the PSW The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of the PSW basically represents the arithmetic status of the CPU, the upper byte of the PSW controls the interrupt system of the INCA-D and the arbitration mechanism for the external bus interface. Note: Pipeline effects have to be considered when enabling/disabling interrupt requests via modifications of register PSW (see chapter “The Central Processing Unit”). Data Sheet 102 2003-03-31 INCA-D PSB 21473 Interrupts PSW (FF10H / 88H) 15 SFR 14 13 12 Reset Value: 00H 11 10 9 8 ILVL IEN 0 0 0 rw rw r r r 7 6 5 4 3 2 1 0 0 0 MULIP E Z V C N r r rw rw rw rw rw rw Bit Function N, C, V, Z, E, MULIP CPU status flags (Described in section “The Central Processing Unit”, page 53). Define the current status of the CPU (ALU, multiplication unit). ILVL CPU Priority Level Defines the current priority level for the CPU FH: Highest priority level 0H: Lowest priority level IEN Interrupt Enable Control Bit (globally enables/disables interrupt requests) ‘0’: Interrupt requests are disabled ‘1’: Interrupt requests are enabled CPU Priority ILVL defines the current level for the operation of the CPU. This bit field reflects the priority level of the routine that is currently executed. Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced. The PSW is saved on the system stack before. The CPU level determines the minimum interrupt priority level that will be serviced. Any request on the same or a lower level will not be acknowledged. The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged. PEC transfers do not really interrupt the CPU, but rather “steal” a single cycle, so PEC services do not influence the ILVL field in the PSW. Hardware traps switch the CPU level to maximum priority (ie. 15) so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed. Note: The TRAP instruction does not change the CPU level, so software invoked trap service routines may be interrupted by higher requests. Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU. When IEN is cleared, no interrupt requests are accepted by the CPU. When IEN is set to '1', all interrupt sources, which have been Data Sheet 103 2003-03-31 INCA-D PSB 21473 Interrupts individually enabled by the interrupt enable bits in their associated control registers, are globally enabled. Note: Traps are non-maskable and are therefore not affected by the IEN bit. 8.4 Operation of the PEC Channels The INCA-D's Peripheral Event Controller (PEC) provides 8 PEC service channels, which move a single byte or word between two locations in the whole memory space. This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request (eg. serial channels, etc.). Each channel is controlled by a dedicated PEC Channel Counter/Control register (PECCx) and a pair of pointers for source (SRCPx) and destination (DSTPx) of the data transfer. For further details regarding Extended PEC transfers refer to Chapter 6.3. The PECC registers control the action that is performed by the respective PEC channel. Data Sheet 104 2003-03-31 INCA-D PSB 21473 Interrupts PECCx (FECyH / 6zH, see table) 15 14 13 12 11 - - - - - SFR 10 9 INC 8 7 BWT rw Reset Value: 0000H 6 rw 5 4 3 2 COUNT 1 0 rw Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel’s action (see table below) BWT Byte / Word Transfer Selection 0: Transfer a Word 1: Transfer a Byte INC Increment Control (Modification of SRCPx or DSTPx) 0 0: Pointers are not modified 0 1: Increment DSTPx by 1 or 2 (BWT) 1 0: Increment SRCPx by 1 or 2 (BWT) 1 1: Reserved. Do not use this combination. (changed to 10 by hardware) PEC Control Register Addresses Register Address Reg. Space Register Address Reg. Space PECC0 FEC0H / 60H SFR PECC4 FEC8H / 64H SFR PECC1 FEC2H / 61H SFR PECC5 FECAH / 65H SFR PECC2 FEC4H / 62H SFR PECC6 FECCH / 66H SFR PECC3 FEC6H / 63H SFR PECC7 FECEH / 67H SFR Byte/Word Transfer bit BWT controls, if a byte or a word is moved during a PEC service cycle. This selection controls the transferred data size and the increment step for the modified pointer. Increment Control Field INC controls, if one of the PEC pointers is incremented after the PEC transfer. It is not possible to increment both pointers, however. If the pointers are not modified (INC=’00’), the respective channel will always move data from the same source to the same destination. Note: The reserved combination ‘11’ is changed to ‘10’ by hardware. However, it is not recommended to use this combination. The PEC Transfer Count Field COUNT controls the action of a respective PEC channel, where the content of bit field COUNT at the time the request is activated selects the action. COUNT may allow a specified number of PEC transfers, unlimited transfers or no PEC service at all. Data Sheet 105 2003-03-31 INCA-D PSB 21473 Interrupts The table below summarizes, how the COUNT field itself, the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT. • Previous Modified COUNT COUNT IR after PEC Action of PEC Channel and Comments service FFH FFH ‘0’ Move a Byte / Word Continuous transfer mode, ie. COUNT is not modified FEH..02H FDH..01H ‘0’ Move a Byte / Word and decrement COUNT 01H 00H ‘1’ Move a Byte / Word Leave request flag set, which triggers another request 00H 00H (‘1’) No action! Activate interrupt service routine rather than PEC channel. The PEC transfer counter allows to service a specified number of requests by the respective PEC channel, and then (when COUNT reaches 00H) activate the interrupt service routine, which is associated with the priority level. After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced. Continuous transfers are selected by the value FFH in bit field COUNT. In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again. When COUNT is decremented from 01H to 00H after a transfer, the request flag is not cleared, which generates another request from the same source. When COUNT already contains the value 00H, the respective PEC channel remains idle and the associated interrupt service routine is activated instead. This allows to choose, if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine. Note: PEC transfers are only executed, if their priority level is higher than the CPU level, ie. only PEC channels 7...4 are processed, while the CPU executes on level 14. All interrupt request sources that are enabled and programmed for PEC service should use different channels. Otherwise only one transfer will be performed for all simultaneous requests. When COUNT is decremented to 00H, and the CPU is to be interrupted, an incorrect interrupt vector will be generated. The source and destination pointers specifiy the locations between which the data is to be moved. A pair of pointers (SRCPx and DSTPx) is associated with each of the 8 PEC channels. These pointers do not reside in specific SFRs, but are mapped into the internal RAM of the INCA-D just below the bit-addressable area (see figure below). Data Sheet 106 2003-03-31 INCA-D PSB 21473 Interrupts • Figure 8-6 DSTP7 00’FCFEH DSTP3 00’FCEEH SRCP7 00’FCFCH SRCP3 00’FCECH DSTP6 00’FCFAH DSTP2 00’FCEAH SRCP6 00’FCF8H SRCP2 00’FCE8H DSTP5 00’FCF6H DSTP1 00’FCE6H SRCP5 00’FCF4H SRCP1 00’FCE4H DSTP4 00’FCF2H DSTP0 00’FCE2H SRCP4 00’FCF0H SRCP0 00’FCE0H Mapping of PEC Pointers into the Internal RAM The pointer locations for inactive PEC channels may be used for general data storage. Only the required pointers occupy RAM locations. Note: If word data transfer is selected for a specific PEC channel (ie. BWT=’0’), the respective source and destination pointers must both contain a valid word address which points to an even byte boundary. Otherwise the Illegal Word Access trap will be invoked, when this channel is used. 8.5 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled, so they are arbitrated and serviced (if they win), or they may be disabled, so their requests are disregarded and not serviced. Enabling and disabling interrupt requests may be done via three mechanisms: Control Bits allow to switch each individual source “ON” or “OFF”, so it may generate a request or not. The control bits (xxIE) are located in the respective interrupt control registers. All interrupt requests may be enabled or disabled generally via bit IEN in register PSW. This control bit is the “main switch” that selects, if requests from any source are accepted or not. For a specific request to be arbitrated the respective source’s enable bit and the global enable bit must both be set. The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged, disclosing all other requests. The priority level of the source that won the arbitration is compared against the CPU’s current level and the source is only serviced, if its level is higher than the current CPU level. Data Sheet 107 2003-03-31 INCA-D PSB 21473 Interrupts Changing the CPU level to a specific value via software blocks all requests on the same or a lower level. An interrupt source that is assigned to level 0 will be disabled and never be serviced. The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1...4 instructions. This is useful eg. for semaphore handling and does not require to re-enable the interrupt system after the unseparable instruction sequence. Interrupt Class Management An interrupt class covers a set of interrupt sources with the same importance, ie. the same priority from the system’s viewpoint. Interrupts of the same class must not interrupt each other. The INCA-D supports this function with two features: Classes with up to 4 members can be established by using the same interrupt priority (ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality is built-in and handled automatically by the interrupt controller. Classes with more than 4 members can be established by using a number of adjacent interrupt priorities (ILVL) and the respective group levels (4 per ILVL). Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class. All requests from the same or any lower level are blocked now, ie. no request of this class will be accepted. The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities, depending on the number of members in a class. A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8, which is the highest priority (ILVL) in class 2. Class 1 requests or PEC requests are still serviced in this case. The 19 interrupt sources (excluding PEC requests) are so assigned to 3 classes of priority rather than to 7 different levels, as the hardware support would do. Table 8-5 ILVL (Priority) Software controlled Interrupt Classes (Example) GLVL 3 2 1 Interpretation 0 15 PEC service on up to 8 channels 14 13 12 X 11 X X X X Interrupt Class 1 5 sources on 2 levels 10 9 Data Sheet 108 2003-03-31 INCA-D PSB 21473 Interrupts ILVL (Priority) GLVL Interpretation 3 2 1 0 8 X X X X 7 X X X X 6 X 5 X X X X 4 X Interrupt Class 2 9 sources on 3 levels Interrupt Class 3 5 sources on 2 levels 3 2 1 0 8.6 No service! Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the location, where the execution of the interrupted task is to be resumed after returning from the service routine. This return location is specified through the Instruction Pointer (IP) and, in case of a segmented memory model, the Code Segment Pointer (CSP). Bit SGTDIS in register SYSCON controls, how the return location is stored. The system stack receives the PSW first, followed by the IP (unsegmented) or followed by CSP and then IP (segmented mode). This optimizes the usage of the system stack, if segmentation is disabled. The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request that is to be serviced, so the CPU now executes on the new level. If a multiplication or division was in progress at the time the interrupt request was acknowledged, bit MULIP in register PSW is set to ‘1’. In this case the return location that is saved on the stack is not the next instruction in the instruction flow, but rather the multiply or divide instruction itself, as this instruction has been interrupted and will be completed after returning from the service routine. Data Sheet 109 2003-03-31 INCA-D PSB 21473 Interrupts • Figure 8-7 Task Status saved on the System Stack The interrupt request flag of the source that is being serviced is cleared. The IP is loaded with the vector associated with the requesting source (the CSP is cleared in case of segmentation) and the first instruction of the service routine is fetched from the respective vector location, which is expected to branch to the service routine itself. The data page pointers and the context pointer are not affected. When the interrupt service routine is left (RETI is executed), the status information is popped from the system stack in the reverse order, taking into account the value of bit SGTDIS. Context Switching An interrupt service routine usually saves all the registers it uses on the stack, and restores them before returning. The more registers a routine uses, the more time is wasted with saving and restoring. The INCA-D allows to switch the complete bank of CPU registers (GPRs) with a single instruction, so the service routine executes within its own, separate context. The instruction “SCXT CP, #New_Bank” pushes the content of the context pointer (CP) on the system stack and loads CP with the immediate value “New_Bank”, which selects a new register bank. The service routine may now use its “own registers”. This register bank is preserved, when the service routine terminates, ie. its contents are available on the next call. Before returning (RETI) the previous CP is simply POPped from the system stack, which returns the registers to the original bank. Note: The first instruction following the SCXT instruction must not use a GPR. Data Sheet 110 2003-03-31 INCA-D PSB 21473 Interrupts Resources that are used by the interrupting program must eventually be saved and restored, eg. the DPPs and the registers of the MUL/DIV unit. 8.7 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction (I1) being fetched from the interrupt vector location. The basic interrupt response time for the INCA-D is 3 instruction cycles. • Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N+1 N+2 I1 DECODE N-1 N TRAP (1) TRAP (2) EXECUTE N-2 N-1 N TRAP WRITEBACK N-3 N-2 N-1 N IR-Flag 1 0 Interrupt Response Time Figure 8-8 Pipeline Diagram for Interrupt Response Time All instructions in the pipeline including instruction N (during which the interrupt request flag is set) are completed before entering the service routine. The actual execution time for these instructions (eg. waitstates) therefore influences the interrupt response time. In the figure above the respective interrupt request flag is set in cycle 1 (fetching of instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline, replacing instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes the injected TRAP instruction (save PSW, IP and CSP, if segmented mode) and fetches the first instruction (I1) from the respective vector location. All instructions that entered the pipeline after setting of the interrupt request flag (N+1, N+2) will be executed after returning from the interrupt service routine. The minimum interrupt response time is 5 states (10 TCL). This requires program execution from the internal code memory, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the interrupt request flag is set during the first state of an instruction cycle, the minimum interrupt response time under these conditions is 6 state times (12 TCL). Data Sheet 111 2003-03-31 INCA-D PSB 21473 Interrupts The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine (including N). • When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or instruction N explicitly writes to the PSW or the SP, the minimum interrupt response time may be extended by 1 state time for each of these conditions. • When instruction N reads an operand from the internal code memory, or when N is a call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum interrupt response time may additionally be extended by 2 state times during internal code memory program execution. • In case instruction N reads the PSW and instruction N-1 has an effect on the condition flags, the interrupt response time may additionally be extended by 2 state times. The worst case interrupt response time during internal code memory program execution adds to 12 state times (24 TCL). Any reference to external locations increases the interrupt response time due to pipeline related access priorities. The following conditions have to be considered: • Instruction fetch from an external location • Operand read from an external location • Result write-back to an external location Depending on where the instructions, source and destination operands are located, there are a number of combinations. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: The worst case interrupt response time including external accesses will occur, when instructions N, N+1 and N+2 are executed out of external memory, instructions N-1 and N require external operand read accesses, instructions N-3 through N write back external operands, and the interrupt vector also points to an external location. In this case the interrupt response time is the time to perform 9 word bus accesses, because instruction I1 cannot be fetched via the external bus until all write, fetch and read requests of preceding instructions in the pipeline are terminated. When the above example has the interrupt vector pointing into the internal code memory, the interrupt response time is 7 word bus accesses plus 2 states, because fetching of instruction I1 from internal code memory can start earlier. When instructions N, N+1 and N+2 are executed out of external memory and the interrupt vector also points to an external location, but all operands for instructions N-3 through N are in internal memory, then the interrupt response time is the time to perform 3 word bus accesses. When the above example has the interrupt vector pointing into the internal code memory, the interrupt response time is 1 word bus access plus 4 states. Data Sheet 112 2003-03-31 INCA-D PSB 21473 Interrupts After an interrupt service routine has been terminated by executing the RETI instruction, and if further interrupts are pending, the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted. In most cases two instructions will be executed during this time. Only one instruction will typically be executed, if the first instruction following the RETI instruction is a branch instruction (without cache hit), or if it reads an operand from internal code memory, or if it is executed out of the internal RAM. Note: A bus access in this context includes all delays which can occur during an external bus cycle. 8.8 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started. The basic PEC response time for the INCA-D is 2 instruction cycles. • Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N+1 N+2 N+2 DECODE N-1 N PEC N+1 EXECUTE N-2 N-1 N PEC WRITEBACK N-3 N-2 N-1 N IR-Flag 1 0 PEC Response Time Figure 8-9 Pipeline Diagram for PEC Response Time In Figure 8-9 the respective interrupt request flag is set in cycle 1 (fetching of instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a PEC transfer “instruction” is injected into the decode stage of the pipeline, suspending instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes the injected PEC transfer and resumes the execution of instruction N+1. All instructions that entered the pipeline after setting of the interrupt request flag (N+1, N+2) will be executed after the PEC data transfer. Note: When instruction N reads any of the PEC control registers PECC7...PECC0, while a PEC request wins the current round of prioritization, this round is repeated and the PEC data transfer is started one cycle later. Data Sheet 113 2003-03-31 INCA-D PSB 21473 Interrupts The minimum PEC response time is 3 states (6 TCL). This requires program execution from the internal code memory, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the interrupt request flag is set during the first state of an instruction cycle, the minimum PEC response time under these conditions is 4 state times (8 TCL). The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer (including N). • When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the minimum PEC response time may be extended by 1 state time for each of these conditions. • When instruction N reads an operand from the internal code memory, or when N is a call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum PEC response time may additionally be extended by 2 state times during internal code memory program execution. • In case instruction N reads the PSW and instruction N-1 has an effect on the condition flags, the PEC response time may additionally be extended by 2 state times. The worst case PEC response time during internal code memory program execution adds to 9 state times (18 TCL). Any reference to external locations increases the PEC response time due to pipeline related access priorities. The following conditions have to be considered: • Instruction fetch from an external location • Operand read from an external location • Result write-back to an external location Depending on where the instructions, source and destination operands are located, there are a number of combinations. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: The worst case interrupt response time including external accesses will occur, when instructions N and N+1 are executed out of external memory, instructions N-1 and N require external operand read accesses and instructions N-3, N-2 and N-1 write back external operands. In this case the PEC response time is the time to perform 7 word bus accesses. When instructions N and N+1 are executed out of external memory, but all operands for instructions N-3 through N-1 are in internal memory, then the PEC response time is the time to perform 1 word bus access plus 2 state times. Once a request for PEC service has been acknowledged by the CPU, the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal code memory or external memory and to write the destination operand over the external bus in an external program environment. Data Sheet 114 2003-03-31 INCA-D PSB 21473 Interrupts Note: A bus access in this context includes all delays which can occur during an external bus cycle. 8.9 External Interrupts The INCA-D provides many possibilities to react on external asynchronous events by using dedicated pins or a number of I/O lines for interrupt input. For three of these pins either a positive, a negative, or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request (so called Fast External Interrupts). For five of these pins (External Interrupts 3-7 at Port 2) a rising edge, a falling edge or a detected high level on the interrupt request line cause an interrupt or PEC request. • Table 8-6 Pins to be used as External Interrupt Inputs Port Pin Original Function Control Register P2.0 Fast External Interrupt 0 EXICON P2.1 Fast External Interrupt 1 EXICON P2.2 Fast External Interrupt 2 EXICON P2.3 External Interrupt 3 IRQ14_STA P2.4 External Interrupt 4 IRQ14_STA P2.5 External Interrupt 5 IRQ14_STA P2.6 External Interrupt 6 IRQ14_STA P2.7 External Interrupt 7 IRQ14_STA P3.7 Auxiliary timer T2 input pin T2CON P3.5 Auxiliary timer T4 input pin T4CON Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode. This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or T4CON to 101B. The active edge of the external input signal is determined by bit fields T2I or T4I. When these fields are programmed to X01B, interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or T4IN, respectively. When T2I or T4I are programmed to X10B, then a negative external transition will set the corresponding request flag. When T2I or T4I are programmed to X11B, both a positive and a negative transition will set the request flag. In all three cases, the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN. When the interrupt Data Sheet 115 2003-03-31 INCA-D PSB 21473 Interrupts enable bits T2IE or T4IE are set, a PEC request or an interrupt request for vector T2INT or T4INT will be generated. Note: The non-maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU to react on an external input signal. NMI and RSTIN are dedicated input pins, which cause hardware traps. Regular External Interrupts at P2.3-7 The input pins that may be used for regular external interrupts are sampled every 16 TCL, ie. external events are scanned and detected in timeframes of 16 TCL. These five pins of Port 2 (P2.3...P2.7) can individually be programmed to determine the sensitivity, i.e. rising, falling or level sensitivity can be selected. REXICON (00DF38H) Reset value: 0000H 15 14 13 12 11 10 - - - - - - 7 6 5 4 3 2 9 8 RE7LS2 RE7LS1 rw rw 1 0 RE6LS2 RE6LS1 RE5LS2 RE5LS1 RE4LS2 RE4LS1 RE3LS2 RE3LS1 rw rw rw rw rw rw rw rw • Bit RExLSn Function Regular External Interrupt x Level Sensitivity 0 0: Interrupt on positive edge (rising) 0 1: Interrupt on negative edge (falling) 1 0: Interrupt on level detection, i.e. detected level is HIGH 1 1: Interrupt on level detection, i.e. detected level is HIGH Fast External Interrupts The INCA-D provides the capability to sample selected interrupt pins every 2 TCL, so external events are captured faster than with standard interrupt inputs. Three pins of Port 2 (P2.2...P2.0) can individually be programmed to this fast interrupt mode, where also the trigger transition (rising, falling or both) can be selected. The External Interrupt Control register EXICON controls this feature for all 3 pins. Data Sheet 116 2003-03-31 INCA-D PSB 21473 Interrupts EXICON (F1C0H / E0H) 15 14 13 - 12 ESFR 11 - 10 9 - 8 Reset Value: 0000H 7 - 6 5 4 3 2 1 0 EXI2ES EXI1ES EXI0ES rw rw rw - Bit Function EXIxES External Interrupt x Edge Selection Field (x=7...0) 0 0: Fast external interrupts disabled 0 1: Interrupt on positive edge (rising) 1 0: Interrupt on negative edge (falling) 1 1: Interrupt on any edge (rising or falling) Note: The fast external interrupt inputs are sampled every 2 TCL. The interrupt request arbitration and processing, however, is executed every 8 TCL. The interrupt control registers listed below (FEI2IC..FEI0IC) control the fast external interrupts of the INCA-D. FEIxIC (See Table) 15 14 13 SFR 12 11 10 9 8 Reset Value: - - 00H 7 6 FEIx FEIx IR IE - - - - - - - - rw rw 5 4 3 2 1 0 ILVL GLVL rw rw Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Table 8-7 Fast External Interrupt Control Register Addresses Register Address External Interrupt FEI0IC FF88H / C4H FEX0IN FEI1IC FF8AH / C5H FEX1IN FEI2IC FF8CH / C6H FEX2IN 8.10 Trap Functions Traps interrupt the current execution similar to standard interrupts. However, trap functions offer the possibility to bypass the interrupt system's prioritization process in cases where immediate system reaction is required. Trap functions are not maskable and always have priority over interrupt requests on any priority level. Data Sheet 117 2003-03-31 INCA-D PSB 21473 Interrupts The INCA-D provides two different kinds of trapping mechanisms. Hardware traps are triggered by events that occur during program execution (eg. illegal access or undefined opcode), software traps are initiated via an instruction within the current execution flow. Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine. The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00’0000H through 00’01FCH will be branched to. Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occurred. PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and a jump is taken to the specified vector location. When segmentation is enabled and a trap is executed, the CSP for the trap service routine is set to code segment 0. No Interrupt Request flags are affected by the TRAP instruction. The interrupt service routine called by a TRAP instruction must be terminated with a RETI (return from interrupt) instruction to ensure correct operation. Note: The CPU level in register PSW is not modified by the TRAP instruction, so the service routine is executed on the same priority level from which it was invoked. Therefore, the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts, other than when triggered by a hardware trap. Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program (not identified at assembly time). A hardware trap may also be triggered intentionally, eg. to emulate additional instructions by generating an Illegal Opcode trap. The INCA-D distinguishes eight different hardware trap functions. When a hardware trap condition has been detected, the CPU branches to the trap vector location for the respective trap condition. Depending on the trap condition, the instruction which caused the trap is either completed or cancelled (ie. it has no effect on the system state) before the trap handling routine is entered. Hardware traps are non-maskable and always have priority over every other CPU activity. If several hardware trap conditions are detected within the same instruction cycle, the highest priority trap is serviced (see table in section “Interrupt System Structure”). PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level (ie. level 15), disabling all interrupts. The CSP is set to code segment zero, if segmentation is enabled. A trap service routine must be terminated with the RETI instruction. The eight hardware trap functions of the INCA-D are divided into two classes: Data Sheet 118 2003-03-31 INCA-D PSB 21473 Interrupts Class A traps are • external Non-Maskable Interrupt (NMI) • Stack Overflow • Stack Underflow trap These traps share the same trap priority, but have an individual vector address. Class B traps are • • • • • Undefined Opcode Protection Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Trap These traps share the same trap priority, and the same vector address. The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the kind of trap which caused the exception. Each trap function is indicated by a separate request flag. When a hardware trap occurs, the corresponding request flag in register TFR is set to '1'. Data Sheet 119 2003-03-31 INCA-D PSB 21473 Interrupts TFR (FFACH / D6H) 15 14 NMI STK OF rw rw 13 SFR 12 11 10 9 8 7 6 5 4 - - - - UND OPC - - - - - - - rw - - - STK OCD UF SF rw Reset Value: 0000H rw 3 2 PRT ILL FLT OPA rw 1 0 ILL INA ILL BUS rw rw rw Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with no external bus defined. ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted. ILLOPA Illegal Word Operand Access Flag A word operand access (read or write) to an odd address has been attempted. PRTFLT Protection Fault Flag A protected instruction with an illegal format has been detected. UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid INCA-D opcode. OCDSF OCDS Flag An OCDS trap has been detected STKUF Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN. STKOF Stack Overflow Flag The current stack pointer value falls below the content of register STKOV. NMI Non Maskable Interrupt Flag A negative transition (falling edge) has been detected on pin NMI. Note: The trap service routine must clear the respective trap flag, otherwise a new trap will be requested after exiting the service routine. Setting a trap request flag by software causes the same effects as if it had been set by hardware. The reset functions (hardware, software, watchdog) may be regarded as a type of trap. Reset functions have the highest system priority (trap priority III). Class A traps have the second highest priority (trap priority II), on the 3rd rank are class B traps, so a class A trap can interrupt a class B trap. If more than one class A trap occur at a time, they are prioritized internally, with the NMI trap on the highest and the stack underflow trap on the lowest priority. All class B traps have the same trap priority (trap priority I). When several class B traps get active at a time, the corresponding flags in the TFR register are set and the trap service routine is entered. Since all class B traps have the same vector, the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine. Data Sheet 120 2003-03-31 INCA-D PSB 21473 Interrupts A class A trap occurring during the execution of a class B trap service routine will be serviced immediately. During the execution of a class A trap service routine, however, any class B trap occurring will not be serviced until the class A trap service routine is exited with a RETI instruction. In this case, the occurrence of the class B trap condition is stored in the TFR register, but the IP value of the instruction which caused this trap is lost. In the case where e.g. an Undefined Opcode trap (class B) occurs simultaneously with an NMI trap (class A), both the NMI and the UNDOPC flag is set, the IP of the instruction with the undefined opcode is pushed onto the system stack, but the NMI trap is executed. After return from the NMI service routine, the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap. External NMI Trap Whenever a high to low transition on the dedicated external NMI pin (Non-Maskable Interrupt) is detected, the NMI flag in register TFR is set and the CPU will enter the NMI trap routine. The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap. Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV, the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine. Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP. When an implicit decrement of the SP is made through a PUSH or CALL instruction, or upon interrupt or trap entry, the IP value pushed is the address of the following instruction. When the SP is decremented by a subtract instruction, the IP value pushed represents the address of the instruction after the instruction following the subtract instruction. For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state (PSW, IP, in segmented mode also CSP) twice. Otherwise, a system reset should be generated. Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN, the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine. Again, which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP. When an implicit increment of the SP is made through a POP or return instruction, the IP value pushed is the address of the following instruction. When the SP is incremented by an add instruction, the pushed IP value represents the address of the instruction after the instruction following the add instruction. Data Sheet 121 2003-03-31 INCA-D PSB 21473 Interrupts Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid INCA-D opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine. The IP value pushed onto the system stack is the address of the instruction that caused the trap. This can be used to emulate unimplemented instructions. The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP. In order to resume processing, the stacked IP value must be incremented by the size of the undefined instruction, which is determined by the user, before a RETI instruction is executed. Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode, the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine. The protected instructions include DISWDT, EINIT, IDLE, PWRDN, SRST, and SRVWDT. The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap. Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address, the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap. Illegal Instruction Access Trap Whenever a branch is made to an odd byte address, the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine. The IP value pushed onto the system stack is the illegal odd target address of the branch instruction. Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch, data read or data write, and no external bus configuration has been specified, the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap. Data Sheet 122 2003-03-31 INCA-D PSB 21473 Parallel Ports 9 Parallel Ports The INCA-D features Port 0 (inculdes 8 bit P0H and 8 bit P0L), Port 1 (8 bit P1H and 8 bit P1L), Port 2 (14 bit), Port 3 (16 bit), Port 4 (6 bit), Port 6 (3 bit) and Port 7 (10 bit). The I/O ports are true bidirectional ports and may be used for general purpose Input/ Output controlled via software or may be used implicitly by INCA-D’s integrated peripherals or the External Bus Controller. All port lines are bit addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. Internal pull transistors are connected to the ports if the corresponding bits of register PxPUDEN are set to ’1’ . Either a pull down or a pull up transistors will be selected via register PxPUDSEL. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. A write operation to a port pin configured as an input (DPx.y = ’0’) causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A read-modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. General Remark for all register descriptions: Unused register bits always have an undefined reset value. The reset value for a whole register in hexadecimal notation does not apply to unused bits. Unused bits may be ’0’, ’1’, or ’-’. Only if indicated with ’-’ , a bit can be written as ’1’ or ’0’; in all other cases the predefined value must be written. Data Sheet 123 2003-03-31 INCA-D PSB 21473 Parallel Ports • Data Input / Output Registers Direction Control Registers Open Drain Control Registers Pull Up/Down Control & Alternate Select Registers P0L DP0LE ODP0L PxPUDSEL: P0H DP0HE ODP0H P1L DP1LE ODP1L P1H DP1HE ODP1H x=0L, 0H, 1L, 1H, 2-7 PxPUDEN: P2 DP2 ODP2 P3 DP3 ODP3 P4 ODP4 PxPHEN: P6 DP4 DP6 ODP6 P7 DP7 ODP7 x=0L,0H,1L,1H 1-7 Figure 9-1 x=0L, 0H, 1L, 1H, 2-7 PxALTSEL1: PxALTSEL0: x=2, 3 x=2, 3, 7 SFRs and Pins associated with the Parallel Ports Output Driver Modes In the INCA-D the ports provide Open Drain Control, which allows to switch the output driver of a port pin from a push/pull configuration to an open drain configuration. In push/ pull mode a port output driver has an upper and a lower transistor, thus it can actively drive the line either to a high or a low level. Figure 9-2 Data Sheet Output Drivers in Push/Pull Mode and in Open Drain Mode 124 2003-03-31 INCA-D PSB 21473 Parallel Ports In open drain mode the upper transistor is always switched off, and the output driver can only actively drive the line to a low level. When writing a ‘1’ to the port latch, the lower transistor is switched off and the output enters a high-impedance state. The high level can then be provided by using an internal pull up transisitor or by an external pull up device. With this feature, it is possible to connect several port pins together to a WiredAND configuration, saving external glue logic and/or additional software overhead for enabling/disabling output signals. This last feature is controlled through the respective Open Drain Control Registers ODPx. These registers allow the individual bit-wise selection of the open drain mode for each port line. If the respective control bit ODPx.y is ‘0’ (default after reset), the output driver is in the push/pull mode. If ODPx.y is ‘1’, the open drain configuration is selected. Note that all ODPx registers are located in the ESFR space. The output driver is disabled in power down mode unless PxPHEN.y = ’1’. Alternate Port Functions Beside the use as general purpose I/Os, each port line has one or more programmable alternate input or output function associated. Whether a port pin should operate as general purpose I/O or as alternate function, is determined by setting the corresonding bit in the PxALTSEL0 register, if the alternate function is not controlled by the corresponding peripheral itself. If a port pin has a second alternate function which has to be selected per software, the bit of the PxALTSEL1 register has to be set accordingly. Note: If two or more alternate functions are enabled concurrently, the behaviour is not predictable, but the device won’t be damaged. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. Note: In this case, make sure DP0 ’ ’0’.. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. When using port pins for general purpose output, the initial output value should be written to the port latch prior to enabling the output drivers, in order to avoid undesired transitions on the output pins. This applies to single pins as well as to pin groups (see examples below). Data Sheet 125 2003-03-31 INCA-D PSB 21473 Parallel Ports OUTPUT_ENABLE_SINGLE_PIN: BSET P4.0 BSET DP4.0 OUTPUT_ENABLE_PIN_GROUP: BFLDL P4, #05H, #05H BFLDL DP4, #05H, #05H ;Initial output level is ’high’ ;Switch on the output driver ;Initial output level is ’high’ ;Switch on the output drivers Note: When using several BSET pairs to control more pins of one port, these pairs must be separated by instructions, which do not reference the respective port (see “Particular Pipeline Effects” in chapter “The Central Processing Unit”). Each of these ports and the alternate input and output functions are described in detail in the following subsections. However, the port structure is similar as described in Figure 9-3 for port 3. •. MUX ’1’ Alternate Function Select MUX Figure 9-3 Data Sheet Port structure 126 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.1 PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halfs of PORT0 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used for general purpose IO, the direction of each line can be configured via the corresponding direction registers DP0H and DP0L. Each port line of P0L and P0H can be switched into push/pull or open drain mode via the open drain control register ODP0H. An internal pull transistor is connected to the pad if bits of register P0xPUDEN = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P0xPUDSEL. The output driver is disabled in power down mode unless P0xPHEN = ’1’. After reset all bits of P0xPUDEN and P0xPUDSEL are set to ’1’ except P0LPUDSEL.6 and P0HPUDSEL.2. While this feature allows to start without any external pull device, the configuration may be overwritten by external pull devices. In this case the internal pull resistors should be disabled by software after reset. Data Sheet 127 2003-03-31 INCA-D PSB 21473 Parallel Ports P0L (FF00H / 80H) 15 14 13 SFR 12 11 10 9 8 Reset Value: - - 00 7 6 5 4 3 2 1 0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 - - - - - - - - P0H (FF02H / 81H) 15 14 13 rw rw rw rw SFR 12 11 10 9 8 rw rw rw rw Reset Value: - - 00 7 6 5 4 3 2 1 0 P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 - - - - - - - - rw Bit Function P0X.y Port data register P0H or P0L bit y DP0L (F100H / 80H) 15 14 13 rw rw rw ESFR 12 11 10 9 8 7 rw rw rw rw Reset Value: - - 00H 6 5 4 3 2 1 0 DP0L DP0L DP0L DP0L DP0L DP0L DP0L DP0L .7 .6 .5 .4 .3 .2 .1 .0 - - - - - - - DP0H (F102H / 81H) 15 14 13 - rw rw rw rw ESFR 12 11 10 9 8 7 rw rw rw rw Reset Value: - - 00H 6 5 4 3 2 1 0 DP0H DP0H DP0H DP0H DP0H DP0H DP0H DP0H .7 .6 .5 .4 .3 .2 .1 .0 - - - - - - - - rw rw rw rw Bit Function DP0X.y Port direction register DP0H or DP0L bit y DP0X.y = 0: Port line P0X.y is an input (high-impedance) DP0X.y = 1: Port line P0X.y is an output Data Sheet 128 rw rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports ODP0L (FE20H / 10H) 15 14 13 12 SFR 11 10 9 8 Reset Value: - - 00H 7 6 5 4 3 2 1 0 ODP0 ODP0 ODP0 ODP0 ODP0 ODP0 ODP0 ODP0 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0 - - - - - - - - ODP0H (FE22H / 11H) 15 14 13 12 rw rw rw rw SFR 11 10 9 8 rw rw rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 ODP0 ODP0 ODP0 ODP0 ODP0 ODP0 ODP0 ODP0 H.7 H.6 H.5 H.4 H.3 H.2 H.1 H.0 - - - - - - - - rw rw rw rw rw Bit Function ODP0X.y Port0XOpen Drain control register bit y ODP0X.y = 0: Port line P0X.y output driver in push/pull mode ODP0X.y = 1: Port line P0X.y output driver in open drain mode P0LPUDSEL (FE60H / 30H) 14 13 12 11 10 9 8 - - - - - - - - P0HPUDSEL (FE62H / 31H) 14 13 12 11 10 9 8 - - - - - - - - rw rw rw rw rw rw rw rw Reset Value: - - E3H1) 7 6 5 4 3 2 1 0 P0H P0H P0H P0H P0H P0H P0H P0H PUD PUD PUD PUD PUD PUD PUD PUD SEL.7 SEL.6 SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 rw rw rw rw rw rw rw Bit Function P0xPUDSEL.y Pulldown/Pullup Selection P0xPUDSEL.y = 0: internal programmable pulldown transistor is selected P0xPUDSEL.y = 1: internal programmable pullup transistor is selected 1) rw 7 6 5 4 3 2 1 0 P0L P0L P0L P0L P0L P0L P0L P0L PUD PUD PUD PUD PUD PUD PUD PUD SEL.7 SEL.6 SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 SFR 15 rw Reset Value: - -3F1)H SFR 15 rw rw The reset value determines also the memory bus configuration after reset. For details refer to Chapter 24.8 Data Sheet 129 2003-03-31 INCA-D PSB 21473 Parallel Ports P0LPUDEN (FE64H / 32H) SFR 15 14 13 12 11 10 9 8 - - - - - - - - P0HPUDEN (FE66H / 33H) Reset Value: - - FFH 7 6 5 4 3 2 1 0 P0L P0L P0L P0L P0L P0L P0L P0L PUD PUD PUD PUD PUD PUD PUD PUD EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 rw rw rw rw SFR 15 14 13 12 11 10 9 8 - - - - - - - - rw rw 7 6 5 4 3 2 1 0 P0H P0H P0H P0H P0H P0H P0H P0H PUD PUD PUD PUD PUD PUD PUD PUD EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 rw rw rw rw rw rw Function P0xPUDEN.y Pulldown/Pullup Enable P0xPUDEN.y = 0: internal programmable pull transistor is disabled P0xPUDEN.y = 1: internal programmable pull transistor is enabled SFR 15 14 13 12 11 10 9 8 - - - - - - - - P0HPHEN (FE6AH / 35H) 14 13 12 11 10 9 8 - - - - - - - - rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 P0L P0L P0L P0L P0L P0L P0L P0L PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN .6 .5 .4 .3 .2 .1 .0 .7 rw rw rw rw SFR 15 rw Reset Value: - - FFH Bit P0LPHEN (FE68H / 34H) rw rw rw rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 P0H P0H P0H P0H P0H P0H P0H P0H PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw Bit Function P0xPHEN.y Output Driver Enable in Power Down Mode P0xPHEN.y = 0: output driver is disabled in power down mode P0xPHEN.y = 1: output driver is enabled in power down mode Data Sheet 130 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.1.1 Alternate Functions of PORT0 For external memory access PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode is enabled). PORT0 is also used to select the system startup configuration. During reset, PORT0 is configured to input, and each line is held high through an internal pullup device. Each line can now be individually pulled to a low level (see DC-level specifications in the respective Data Sheets) through an external pulldown device. A default configuration is selected when the respective PORT0 lines are at a high level. Through pulling individual lines to a low level, this default can be changed according to the needs of the applications. The internal pullup devices are designed such that an external pulldown resistors (see specification) can be used to apply a correct low level. These external pulldown resistors can remain connected to the PORT0 pins also during normal operation, however, care has to be taken such that they do not disturb the normal function of PORT0 (this might be the case, for example, if the external resistor is too strong). With the end of reset, the selected bus configuration will be written to the BUSCON0 register. The configuration of the high byte of PORT0, will be copied into the special register RP0H. This read-only register holds the selection for the number of chip selects and segment addresses. Software can read this register in order to react according to the selected configuration, if required. Note: When the reset is terminated, the internal pullup devices must be switched off by Software using bit BCLR of register P0(L/H)PUDEN.x, and PORT0 will be switched to the appropriate operating mode. During external accesses in multiplexed bus modes PORT0 first outputs the 16-bit intrasegment address as an alternate output function. PORT0 is then switched to highimpedance input mode to read the incoming instruction or data. In 8-bit data bus mode, two memory cycles are required for word accesses, the first for the low byte and the second for the high byte of the word. During write cycles PORT0 outputs the data byte or word after outputting the address. During external accesses in demultiplexed bus modes PORT0 reads the incoming instruction or data word or outputs the data byte or word. Data Sheet 131 2003-03-31 INCA-D PSB 21473 Parallel Ports Alternate Function a) b) P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 D7 D6 D5 D4 D3 D2 D1 D0 General Purpose Input/Output 8-bit Demux Bus P0H PORT0 P0L Figure 9-4 c) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit Demux Bus d) AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 8-bit MUX Bus AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 16-bit MUX Bus PORT0 I/O and Alternate Functions For external memory access the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled “Alternate Data Output” via a multiplexer. The alternate data can be the 16-bit intrasegment address or the 8/16-bit data information. The incoming data on PORT0 is read on the line “Alternate Data Input”. The user software should not write to the port output latch, otherwise unpredictable results may occur. Figure 9-4 shows the structure of a PORT0 pin. 9.2 PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halfs of PORT1 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used for general purpose IO, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP1L and ODP1H. An internal pull transistor is connected to the pad if bits of register P1xPUDEN.y = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P1xPUDSEL. The output driver is disabled in power down mode unless P1xPHEN = ’1’. After reset, the bits of P1xPUDEN and P1xPUDSEL are set to ’1’. Data Sheet 132 2003-03-31 INCA-D PSB 21473 Parallel Ports P1L (FF04H / 82H) 15 14 13 SFR 12 11 10 9 8 Reset Value: - - 00H 7 6 5 4 3 2 1 0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 - - - - - - - - P1H (FF06H / 83H) 15 14 13 rw rw rw rw SFR 12 11 10 9 8 rw rw rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0 - - - - - - - - rw Bit Function P1X.y Port data register P1H or P1L bit y DP1L (F104H / 82H) 15 14 13 rw rw rw ESFR 12 11 10 9 8 7 rw rw rw rw Reset Value: - - 00H 6 5 4 3 2 1 0 DP1L DP1L DP1L DP1L DP1L DP1L DP1L DP1L .7 .6 .5 .4 .3 .2 .1 .0 - - - - - - - DP1H (F106H / 83H) 15 14 13 - rw rw rw rw ESFR 12 11 10 9 8 7 rw rw rw rw Reset Value: - - 00H 6 5 4 3 2 1 0 DP1H DP1H DP1H DP1H DP1H DP1H DP1H DP1H .7 .6 .5 .4 .3 .2 .1 .0 - - - - - - - - rw rw rw rw Bit Function DP1X.y Port direction register DP1H or DP1L bit y DP1X.y = 0: Port line P1X.y is an input (high-impedance) DP1X.y = 1: Port line P1X.y is an output Data Sheet 133 rw rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports ODP1L (FE24H / 12H) 15 14 13 12 SFR 11 10 9 8 Reset Value: - - 00H 7 6 5 4 3 2 1 0 ODP1 ODP1 ODP1 ODP1 ODP1 ODP1 ODP1 ODP1 L.7 L.6 L.5 L.4 L.3 L.2 L.1 L.0 - - - - - - - - ODP1H (FE26H / 13H) 15 14 13 12 rw rw rw rw SFR 11 10 9 8 rw rw rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 ODP1 ODP1 ODP1 ODP1 ODP1 ODP1 ODP1 ODP1 H.7 H.6 H.5 H.4 H.3 H.2 H.1 H.0 - - - - - - - - rw rw rw rw rw Bit Function ODP1x.y Port1x Open Drain control register bit y ODP1x.y = 0: Port line P1x.y output driver in push/pull mode ODP1x.y = 1: Port line P1x.y output driver in open drain mode P1LPUDSEL (FE6CH / 36H) SFR 15 14 13 12 11 10 9 8 - - - - - - - - P1HPUDSEL (FE6EH / 37H) 14 13 12 11 10 9 8 - - - - - - - - rw 7 6 5 4 3 2 1 0 P1L P1L P1L P1L P1L P1L P1L P1L PUD PUD PUD PUD PUD PUD PUD PUD SEL.7 SEL.6 SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 rw rw rw rw rw rw rw rw Reset Value: - - FFH 7 6 5 4 3 2 1 0 P1H P1H P1H P1H P1H P1H P1H P1H PUD PUD PUD PUD PUD PUD PUD PUD SEL.7 SEL.6 SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 rw rw rw rw rw rw rw Bit Function P1xPUDSEL.y Pulldown/Pullup Selection P1xPUDSEL.y = 0: internal programmable pulldown transistor is selected P1xPUDSEL.y = 1: internal programmable pullup transistor is selected Data Sheet rw Reset Value: - - FFH SFR 15 rw 134 rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P1LPUDEN (FE70H / 38H) SFR 15 14 13 12 11 10 9 8 - - - - - - - - P1HPUDEN (FE72H / 39H) Reset Value: - - FFH 7 6 5 4 3 2 1 0 P1L P1L P1L P1L P1L P1L P1L P1L PUD PUD PUD PUD PUD PUD PUD PUD EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 rw rw rw rw SFR 15 14 13 12 11 10 9 8 - - - - - - - - rw rw 7 6 5 4 3 2 1 0 P1H P1H P1H P1H P1H P1H P1H P1H PUD PUD PUD PUD PUD PUD PUD PUD EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 rw rw rw rw rw rw Function P1xPUDEN.y Pulldown/Pullup Enable P1xPUDEN.y = 0: internal programmable pull transistor is disabled P1xPUDEN.y = 1: internal programmable pull transistor is enabled SFR 15 14 13 12 11 10 9 8 - - - - - - - - P1HPHEN (FE76H / 3BH) 14 13 12 11 10 9 8 - - - - - - - - rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 P1L P1L P1L P1L P1L P1L P1L P1L PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN .0 .1 .2 .3 .4 .5 .7 .6 rw rw rw rw SFR 15 rw Reset Value: - - FFH Bit P1LPHEN (FE74H / 3AH) rw rw rw rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 P1H P1H P1H P1H P1H P1H P1H P1H PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN .7 .6 .5 .4 .3 .2 .1 .0 rw rw rw rw rw Bit Function P1xPHEN.y Output Driver Enable in Power Down Mode P1xPHEN.y = 0: output driver is disabled in power down mode P1xPHEN.y = 1: output driver is enabled in power down mode Data Sheet 135 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.2.1 Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus. Note that demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose IO. During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intrasegment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a demultiplexed bus mode, PORT1 is not used and is available for general purpose IO. • Alternate Function P1H PORT1 P1L P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0 General Purpose Input/Output Figure 9-5 a) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8/16-bit Demux Bus PORT1 I/O and Alternate Functions For external memory access the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output latch is disconnected from the internal bus and is switched to the line labeled “Alternate Data Output” via a multiplexer. The alternate data is the 16-bit intrasegment address. While an external bus mode is enabled, the user software should not write to the port output latch, otherwise unpredictable results may occur. 9.3 PORT2 The Port 2 of INCA-D is an 14-bit port. If Port 2 is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. An internal pull transistor is connected to the pad if register P2PUDEN = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P2PUDSEL. The output driver is disabled in power down mode unless P2PHEN = ’1’. After reset, bits of P2PUDEN and P2PUDSEL are set to ’1’. Data Sheet 136 2003-03-31 INCA-D PSB 21473 Parallel Ports P2 (FFC0H / E0H) 15 14 - - - - SFR 13 12 11 10 9 8 Reset Value: 00 00H 7 6 5 4 3 2 1 0 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 rw rw rw rw rw rw Bit Function P2.y Port data register P2 bit y DP2 (FFC2H / E1H) rw rw rw rw SFR rw rw rw rw Reset Value: 00 00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - DP2 .13 DP2 .12 DP2 .11 DP2 .10 DP2 .9 DP2 .8 DP2 .7 DP2 .6 DP2 .5 DP2 .4 DP2 .3 DP2 .2 DP2 .1 DP2 .0 - - rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function DP2.y Port direction register DP2 bit y DP2.y = 0: Port line P2.y is an input (high-impedance) DP2.y = 1: Port line P2.y is an output ODP2 (F1C2H / E1H) 15 14 - - - - 13 12 SFR 11 10 9 8 Reset Value00 00 7 6 5 4 3 rw rw rw rw rw rw rw rw rw rw rw Function ODP2.y Port 2 Open Drain control register bit y ODP2.y = 0: Port line P2.y output driver in push/pull mode ODP2.y = 1: Port line P2.y output driver in open drain mode P2PUDSEL (FE78H / 3CH) 14 - - - - 1 SFR rw rw rw Reset Value FFFFH 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD - 12SEL.11 SEL.10 SEL.9 SEL.13 SEL. SEL.8 SEL.7 SEL.6 SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P2PUDSEL.y Pulldown/Pullup Selection P2PUDSEL.y = 0: internal programmable pulldown transistor is selected P2PUDSEL.y = 1: internal programmable pullup transistor is selected Data Sheet 0 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 .12 .13 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 .1 .0 Bit 15 2 137 rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P2PUDEN (FE7AH / 3DH) 15 - 14 13 - P2 PUD - EN.13 rw SFR Reset Value: FFFFH 12 11 10 9 8 7 6 5 4 3 2 1 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD EN.-12 EN.11 EN.100 EN.9 EN.8 EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 rw rw rw rw rw rw rw rw rw rw rw Bit Function P2PUDEN.y Pulldown/Pullup Enable P2PUDEN.y = 0: internal programmable pull transistor is disabled P2PUDEN.y = 1: internal programmable pull transistor is enabled P2PHEN (FE7CH / 3EH) 15 14 - - SFR rw Reset Value: 00 00H 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN .9 .13 .12- .11 .7 .10 .6 .3 2 .5 EN.0 .8 .4 rw rw rw rw rw rw rw rw rw rw rw Bit Function P2PHEN.y Output Driver Enable in Power Down Mode P2PHEN.y = 0: output driver is disabled in power down mode P2PHEN.y = 1: output driver is enabled in power down mode P2ALTSEL0 (F122H / 91H) 15 - 14 - P2 ALT SEL0. 13 - - rw 13 12 P2 ALT SEL0. 12 rw 11 P2 ALT SEL0. 11 rw ESFR 10 9 8 7 rw rw rw Reset Value: 00 00H 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 ALT ALT ALT ALT ALT ALT ALT ALT ALT ALT ALT SEL0.9 SEL0. SEL0.8 SEL0.7 SEL0.6SEL0.5 SEL0.4 SEL0.3 SEL0.2 SEL0.1 SEL0.0 10 rw rw rw rw rw rw rw Bit Function P2ALTSEL0.y Alternate Function 0 Selection P2ALTSEL0.y = 0: no alternate function 0 selected P2ALTSEL0.y = 1: alternate function 0 selected Data Sheet rw 0 P2 PUD EN.0 138 rw rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P2ALTSEL1 (F124H / 92H) 15 14 - -- - - 13 - 12 ESFR 11 10 9 8 - - - - - - - - - - 7 Reset Value : --00H 6 5 4 rw rw rw rw Bit Function P2ALTSEL1.y Alternate Function 1Selection P2ALTSEL1.y = 0: no alternate function 1 selected P2ALTSEL1.y = 1: alternate function 1 selected 9.3.1 3 2 P2 P2 P2 P2 P2 P2 ALT ALT ALT ALT ALT ALT SEL1.7 SEL1.6SEL1.5 SEL1.4 SEL1.3 SEL1.2 rw rw 1 0 P2 ALT SEL1.0 - - Alternate Functions of PORT2 The first 3 lines of Port 2 (P2.2..P2.0) serve as Fast External Interrupt inputs (EX2IN...EX0IN) while P2.0 and P2.1 serve also as Serial Data Strobe outputs . The remaining port lines can be used as GPI/O or to multiplex the connected LED field. Table 9-1 summarizes the alternate functions of Port 2. • Table 9-1 Port 2 Alternate Functions Port 2 Pin Alternate Function P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 SDS1/FEX0IN SDS2/FEX1IN FEX2IN LEDMUX(0) LEDMUX(1) LEDMUX(2) LEDMUX(3) LEDMUX(4) LEDMUX(5) LEDMUX(6) LEDMUX(7) LEDMUX(8) LEDMUX(9) LEDMUX(10) Data Sheet Serial Data Strobe 1 or Fast External Interrupt 0 Serial Data Strobe 2 or Fast External Interrupt 1 Fast External Interrupt 2 Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit Output of LED multiplex unit 139 2003-03-31 INCA-D PSB 21473 Parallel Ports Alternate Function Port 2 b) a) P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 LEDMUX10 LEDMUX9 LEDMUX8 LEDMUX7 LEDMUX6 LEDMUX5 LEDMUX4 LEDMUX3 LEDMUX2 LEDMUX1 LEDMUX0 FEX2IN FEX1IN FEX0IN SDS2 SDS1 General Purpose Input/Output Figure 9-6 Data Sheet Port 2 I/O and Alternate Functions 140 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.4 PORT3 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3. All port lines of P3 can be switched into push/pull or open drain mode via the open drain control register ODP3. All port lines support internal pull transistors, which are connected to the pad if register P3PUDEN = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P3PUDSEL. The output driver is disabled in power down mode unless P3PHEN = ’1’. After reset, bits of P3PUDEN and P3PUDSEL are set to ’1’. P3 (FFC4H / E2H) 15 14 13 SFR 12 11 10 9 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 P3.15 P3.14 P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 rw rw rw rw rw rw rw rw Bit Function P3.y Port data register P3 bit y DP3 (FFC6H / E3H) 15 14 DP3 DP3. 14 .15 rw rw rw rw rw rw SFR rw 12 11 10 9 8 7 6 5 4 3 2 1 0 DP3 .13 DP3 .12 DP3 .11 DP3 .10 DP3 .9 DP3 .8 DP3 .7 DP3 .6 DP3 .5 DP3 .4 DP3 .3 DP3 .2 DP3 .1 DP3 .0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw DP3.y Port direction register DP3 bit y DP3.y = 0: Port line P3.y is an input (high-impedance) DP3.y = 1: Port line P3.y is an output ODP3 (F1C6H / E3H) 13 12 ESFR 11 10 9 8 7 Reset Value: 0000H 6 5 4 3 2 1 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 ODP3 .15 .14 .12 .13 .11 .10 .9 .8 .7 .6 .5 .4 .3 .2 .1 rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function ODP3.y Port 3 Open Drain control register bit y ODP3.y = 0: Port line P3.y output driver in push/pull mode ODP3.y = 1: Port line P3.y output driver in open drain mode Data Sheet rw 13 Function 14 rw Reset Value: 0000H Bit 15 rw 141 rw rw 0 rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P3PUDSEL (FE7EH / 3FH) SFR Reset Value: FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU DSEL. DSEL. DSEL. DSEL. DSEL. DSEL. DSEL. DSEL. DSEL. DSEL. DSEL.DSEL. DSEL.DSEL.DSEL. 4 2 1 13 11 10 9 8 7 6 5 3 12 14 15 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P3PUDSEL.y Pulldown/Pullup Selection P3PUDSEL.y = 0: internal programmable pulldown transistor is selected P3PUDSEL.y = 1: internal programmable pullup transistor is selected P3PUDEN (FE80H / 40H) SFR rw Reset Value: FF FFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU P3PU DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. DEN. 14 4 2 1 12 13 11 10 9 8 7 6 5 3 15 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P3PUDEN.y Pulldown/Pullup Enable P3PUDEN.y = 0: internal programmable pull transistor is disabled P3PUDEN.y = 1: internal programmable pull transistor is enabled P3PHEN (FE82H / 41H) 0 SFR 0 rw Reset Value: 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHENPHEN PHEN PHEN .2 .0 .1 .14 .4 .11 .10 .9 .3 .8 .7 .6 .5 .13 .12 .15 rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P3PHEN.y Output Driver Enable in Power Down Mode P3PHEN.y = 0: output driver is disabled in power down mode P3PHEN.y = 1: output driver is enabled in power down mode Data Sheet 142 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P3ALTSEL0 (F126H / 93H) 15 P3 ALT SEL0. 15 rw 14 13 12 P3 ALT SEL0. 14 P3 ALT SEL0. 13 P3 ALT SEL0. 12 rw rw rw ESFR 11 10 P3 P3 ALT ALT SEL0. SEL0 11 rw rw 9 8 7 Reset Value: 0000H 6 5 4 rw rw rw rw rw rw Bit Function P3ALTSEL0.y Alternate Function 0 Selection P3ALTSEL0.y = 0: no alternate function 0 selected P3ALTSEL0.y = 1: alternate function 0 selected P3ALTSEL1 (F128H / 94H) 15 14 13 -- -- P3 ALT SEL1. 13 rw - rw 12 ESFR 11 10 - - - - - - 9 8 7 2 1 0 P3 P3 ALT ALT SEL1.9 SEL1.8 rw rw rw 5 4 3 - - - - - - - - - - Function P3ALTSEL1.y Alternate Function 1 Selection P3ALTSEL.y = 0: no alternate function 1 selected P3ALTSEL.y = 1: alternate function 1 selected 143 rw rw rw Reset Value: 00 00H 6 Bit Data Sheet 3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 ALT ALT ALT ALT ALT ALT ALT ALT ALT ALT SEL0.9SEL0.8 SEL0.7 SEL0.6SEL0.5 SEL0.4 SEL0.3 SEL0.2 SEL0.1 SEL0.0 2 1 0 P3 P3 P3 ALT ALT ALT SEL1.2 SEL1.1 SEL1.0 rw rw - 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.4.1 Alternate Functions of PORT3 The pins of Port 3 serve for various functions. Table 9-2 summarizes the alternate functions of Port 3. • Table 9-2 Alternate Functions of Port 3 Port 3 Pin Alternate Function P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 MRST1/T5IN SSC1 Master Receive / Slave Transmit / Timer 5 Input MTSR1/T4EUD SSC1 Master Transm./ Slave Rec./Timer 4 External Up-Down Input SCLK1/T2EUD SSC1 Shift Clock Input/Output / Timer 2 External up-down Input T3OUT Timer 3 Toggle Output T3EUD Timer 3 External Up/Down Control T4IN Timer 4 Count Input T3IN Timer 3 Count Input T2IN Timer 2 Count Input MRST0/T6IN SSC0 Master Receive / Slave Transmit / Timer 6 Input MTSR0/T5EUD SSC0 Master Transm./ Slave Rec./Timer 5 External Up-Down Input TxD0 ASC Transmit Data Output RxD0 ASC Receive Data Input / Output BHE/WRH Byte High Enable / Write High Output SCLK0/T6EUD SSC0 Shift Clock Input/Output/ Timer 6 External up-down Input T6OUT Timer 3 Toggle Output CAPIN GPT2 Capture Input Alternate Function Port 3 P3.15 P3.14 P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 a) a) CAPIN T6OUT SCLK0 BHE/WRH RxD TxD MTSR0 MRST0 T2IN T3IN T4IN T3EUD T3OUT SCLK1 MTSR1 MRST1 T6EUD T5EUD T6IN T2EUD T4EUD T5IN General Purpose Input/Output Figure 9-7 Data Sheet Port 3 I/O and Alternate Functions 144 2003-03-31 INCA-D PSB 21473 Parallel Ports When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate input function, it reads the input latch, which represents the state of the pin, via the line labeled “Alternate Data Input”. When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to the respective curren Pin P3.12 (BHE/WRH) is one more pin with an alternate output function. However, its structure is slightly different (see figure below), because after reset the BHE or WRH function must be used depending on the system startup configuration. In these cases there is no possibility to program any port latches before. Thus the appropriate alternate function is selected automatically. If BHE/WRH is not used in the system, this pin can be used for general purpose I/O by disabling the alternate function (BYTDIS = ‘1’ / WRCFG=’0’). • x = 15, 12 Figure 9-8 Block Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit DP3.12=’1’ is not required. Data Sheet 145 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.5 PORT4 If this 6-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP4. An internal pull transistor is connected to the pad if register P4PUDEN = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P4PUDSEL. The output driver is disabled in power down mode unless P4PHEN = ’1’. After reset, all bits of P4PUDEN and P4PUDSEL are set to ’1’. P4 (FFC8H / E4H) 15 14 13 SFR 12 11 10 9 8 Reset Value: - - 00H 7 6 5 4 3 2 1 P4.5 P4.4 P4.3 P4.2 P4.1 - - - - - - - Bit Function P4.y Port data register P4 bit y - DP4 (FFCAH / E5H) 15 14 13 - - rw rw SFR 12 11 10 9 8 rw rw rw 0 P4.0 rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0 - - - - - - - - - rw rw rw Bit Function DP4.y Port direction register DP4 bit y DP4.y = 0: Port line P4.y is an input (high-impedance) DP4.y = 1: Port line P4.y is an output ODP4 (F1CAH / E5H) 15 14 13 12 ESFR 11 10 9 8 7 rw rw rw rw Reset Value: - - 00H 6 5 4 3 2 1 0 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 .5 .4 .3 .2 .1 .0 - - Data Sheet - - - - - - - 146 - rw rw rw rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports Bit Function ODP4.y Port 4 Open Drain control register bit y ODP4.y = 0: Port line P4.y output driver in push/pull mode ODP4.y = 1: Port line P4.y output driver in open drain mode P4PUDSEL (FE84H / 42H) SFR Reset Value: - -FFH 15 14 13 12 11 10 9 8 7 6 - - - - - - - - - - 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 PUD PUD PUD PUD PUD PUD SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 rw rw rw rw rw Bit Function P4PUDSEL.y Pulldown/Pullup Selection P4PUDSEL.y = 0: internal programmable pulldown transistor is selected P4PUDSEL.y = 1: internal programmable pullup transistor is selected P4PUDEN (FE86H / 43H) SFR Reset Value: - - FFH 15 14 13 12 11 10 9 8 7 6 - - - - - - - - - - 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 PUD PUD PUD PUD PUD PUD EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 rw rw rw rw Bit Function P4PUDEN.y Pulldown/Pullup Enable P4PUDEN.y = 0: internal programmable pull transistor is disabled P4PUDEN.y = 1: internal programmable pull transistor is enabled P4PHEN (FE88H / 44H) SFR rw rw Reset Value: - - 00H 15 14 13 12 11 10 9 8 7 6 - - - - - - - - - - 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 PHEN PHEN PHEN PHEN PHEN PHEN .5 .4 .3 .2 .1 .0 rw rw rw Bit Function P4PHEN.y Output Driver Enable in Power Down Mode P4PHEN.y = 0: output driver is disabled in power down mode P4PHEN.y = 1: output driver is enabled in power down mode Data Sheet rw 147 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.5.1 Alternate Functions of PORT4 During external bus cycles that use segmentation (ie. an address space above 64 KByte) a number of Port 4 pins may output the segment address lines. The number of pins that is used for segment address output determines the external address space which is directly accessible. The other pins of Port 4 (if any) may be used for general purpose I/O. If segment address lines are selected, the alternate function of Port 4 may be necessary to access eg. external memory directly after reset. For this reason Port 4 will be switched to its alternate function automatically. The number of segment address lines is selected via PORT0 during reset. The selected value can be read from bitfield SALSEL in register RP0H (read only) eg. in order to check the configuration during run time. Table 9-3 summarizes the alternate functions of Port 4 depending on the number of selected segment address lines (coded via bitfield SALSEL). • Table 9-3 Alternate Functions of Port 4 Port 4 Pin Std. Function Altern. Function Altern. Function Altern. Function SALSEL=01 64 KB SALSEL=11 256KB SALSEL=00 1 MB SALSEL=10 4 MB P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O Seg. Address A16 Seg. Address A17 Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O Gen. purpose I/O Seg. Address A16 Seg. Address A17 Seg. Address A18 Seg. Address A19 Gen. purpose I/O Gen. purpose I/O Seg. Address A16 Seg. Address A17 Seg. Address A18 Seg. Address A19 Seg. Address A20 Seg. Address A21 Alternate Function Port 4 - - P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 A21 A20 A19 A18 A17 A16 General Purpose Input/Output Figure 9-9 Data Sheet Port 4 I/O and Alternate Functions 148 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.6 PORT6 If this 3-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP6. An internal pull transistor is connected to the pad if register P6PUDEN = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P6PUDSEL. The output driver is disabled in power down mode unless P6PHEN = ’1’. After reset, all bits of P6PUDEN and P6PUDSEL are set to ’1’. P6 (FFCCH / E6H) 15 14 13 SFR 12 11 10 9 8 Reset Value: - - 00H 7 6 5 4 3 2 1 0 P6.2 P6.1 P6.0 - - - - - - - Bit Function P6.y Port data register P6 bit y - DP6 (FFCEH / E7H) 15 14 13 - - - - SFR 12 11 10 9 8 - rw rw rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 DP6.2 DP6.1 DP6.0 - - - - - - - - - - - - Bit Function DP6.y Port direction register DP6 bit y DP6.y = 0: Port line P6.y is an input (high-impedance) DP6.y = 1: Port line P6.y is an output ODP6 (F1CEH / E7H) 15 14 13 12 ESFR 11 10 9 8 7 - rw rw rw Reset Value: - - 00H 6 5 4 3 2 1 0 ODP6 ODP6 ODP6 .2 .1 .0 - - - - - - - - - - - - - Bit Function ODP6.y Port 6 Open Drain control register bit y ODP6.y = 0: Port line P6.y output driver in push/pull mode ODP6.y = 1: Port line P6.y output driver in open drain mode Data Sheet 149 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P6PUDSEL (FE90H / 48H) SFR Reset Value: - - FFH 15 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - 2 1 0 P6 P6 P6 PUD PUD PUD SEL.2 SEL.1 SEL.0 rw rw Bit Function P6PUDSEL.y Pulldown/Pullup Selection P6PUDSEL.y = 0: internal programmable pulldown transistor is selected P6PUDSEL.y = 1: internal programmable pullup transistor is selected P6PUDEN (FE92H / 49H) SFR Reset Value: - - FFH 15 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - 2 1 0 P6 P6 P6 PUD PUD PUD EN.2 EN.1 EN.0 rw Bit Function P6PUDEN.y Pulldown/Pullup Enable P6PUDEN.y = 0: internal programmable pull transistor is disabled P6PUDEN.y = 1: internal programmable pull transistor is enabled P6PHEN (FE94H / 4AH) SFR 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - rw Function P6PHEN.y Output Driver Enable in Power Down Mode P6PHEN.y = 0: output driver is disabled in power down mode P6PHEN.y = 1: output driver is enabled in power down mode 14 13 12 11 ESFR 10 9 8 rw 2 1 0 P6 P6 P6 PHEN PHEN PHEN .0 .1 .2 Bit 15 rw Reset Value: - - 00H 15 P6ALTSEL0 (F12CH / 96H) rw 7 rw rw Reset Value: - -00H 6 5 4 3 2 1 0 P6 P6 P6 ALT ALT ALT SEL0.2 SEL0.1SEL0.0 - - - - - - - - - - - rw rw rw rw rw Note: If the memory interface has been configured accordingly, the selection of CS0 is done by the External Bus Controller automatically. Data Sheet 150 2003-03-31 INCA-D PSB 21473 Parallel Ports Bit Function P6ALTSEL0.y Alternate Function 0 Selection P6ALTSEL.y = 0: no alternate function 0 selected P6ALTSELy = 1: alternate function 0 selected 9.6.1 Alternate Functions of PORT6 The three chip select signals (CS2..CS0) derived from the bus control registers (BUSCON2...BUSCON0) can be output on 3 pins of Port 6. The number of chip select signals is selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H (read only) eg. in order to check the configuration during run time. Table 9-4 summarizes the alternate functions of Port 6 depending on the number of selected chip select lines (coded via bitfield CSSEL). For information about the coding of 0, 1, or 2 chip-select lines please refer to Table 24-3 on page 24-603. • Table 9-4 Alternate Functions of Port 6 Port 6 Pin Altern. Function P6.0 P6.1 P6.2 Chip select CS0 Chip select CS1 Chip select CS2 Alternate Function Port 6 a) P6.2 P6.1 P6.0 CS2 CS1 CS0 General Purpose Input/Output Figure 9-10 Port 6 I/O and Alternate Functions Data Sheet 151 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.7 PORT7 In the INCA-D Port 10 is an 8-bit general purpose I/O port. The direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP7. An internal pull transistor is connected to the pad if register P7PUDEN = ’1’, no matter whether the INCA-D is in normal operation mode or in power down mode. Either pulldown transistor or pullup transistor will be selected via P7PUDSEL. The output driver is disabled in power down mode unless P7PHEN = ’1’. After reset, all bits of P7PUDEN and P7PUDSEL are set to ’1’. P7 (FFD0H / E8H) 15 14 13 SFR 12 11 10 9 8 7 P7.9 P7.8 - - - - - - rw rw Bit Function P7.y Port data register P7 bit y DP7 (FFD2H / E9H) 15 14 13 Reset Value: - - 00H 6 5 4 11 10 9 8 2 1 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 rw rw rw rw SFR 12 3 rw rw rw 0 P7.0 rw Reset Value: - - 00H 7 6 5 4 3 2 1 0 DP7.9 DP7.8 DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7.0 - - - - - - rw rw rw rw rw rw Bit Function DP7.y Port direction register DP7 bit y DP7.y = 0: Port line P7.y is an input (high-impedance) DP7.y = 1: Port line P7.y is an output ODP7 (F1D2H / E9H) 15 14 13 ESFR 12 11 10 9 8 7 rw rw rw rw Reset Value: - - 00 6 5 4 3 2 1 0 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 .8 .9 .7 .6 .5 .4 .3 .2 .1 .0 - - - - - - rw rw rw rw rw rw rw Bit Function ODP7.y Port 7 Open Drain control register bit y ODP7.y = 0: Port line P7.y output driver in push/pull mode ODP7.y = 1: Port line P7.y output driver in open drain mode Data Sheet 152 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P7PUDSEL (FE96H / 4BH) SFR 15 14 13 12 11 10 - - - - - - Reset Value: - -FFH 9 8 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD SEL.9 SEL.8 SEL.7 SEL.6 SEL.5 SEL.4 SEL.3 SEL.2 SEL.1 SEL.0 rw rw rw rw rw rw rw rw rw Bit Function P7PUDSEL.y Pulldown/Pullup Selection P7PUDSEL.y = 0: internal programmable pulldown transistor is selected P7PUDSEL.y = 1: internal programmable pullup transistor is selected P7PUDEN (FE98H / 4CH) SFR 15 14 13 12 11 10 - - - - - - Reset Value: - - FFH 9 8 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 PUD PUD PUD PUD PUD PUD PUD PUD PUD PUD EN.9 EN.8 EN.7 EN.6 EN.5 EN.4 EN.3 EN.2 EN.1 EN.0 rw rw rw rw rw rw rw rw Bit Function P7PUDEN.y Pulldown/Pullup Enable P7PUDEN.y = 0: internal programmable pull transistor is disabled P7PUDEN.y = 1: internal programmable pull transistor is enabled P7PHEN (FE9AH / 4DH) SFR 15 14 13 12 11 10 - - - - - - rw rw Reset Value: - - 00H 9 8 7 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN PHEN .3 .7 .0 .6 .5 .4 .1 .8 .9 .2 rw rw rw rw rw rw rw Bit Function P7PHEN.y Output Driver Enable in Power Down Mode P7PHEN.y = 0: output driver is disabled in power down mode P7PHEN.y = 1: output driver is enabled in power down mode Data Sheet rw 153 rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports P7ALTSEL0 (F12EAH / 97H) 15 14 13 12 11 ESFR 10 9 8 7 Reset Value: - -00H 6 5 4 3 2 1 0 P7 P7 P7 P7 P7 P7 P7 P7 P7 P7 ALT ALT ALT ALT ALT ALT ALT ALT ALT ALT SEL0.9SEL0.8 SEL0.7 SEL0.6 SEL0.5 SEL0.4 SEL0.3 SEL0.2 SEL0.1 SEL0.0 - - - - - - rw rw rw rw rw Bit Function P7ALTSEL0.y Alternate Function 0 Selection P7ALTSEL.y = 0: no alternate function 0 selected P7ALTSELy = 1: alternate function 0 selected Data Sheet 154 rw rw rw rw rw 2003-03-31 INCA-D PSB 21473 Parallel Ports 9.7.1 Alternate Functions of PORT7 P7(9:0) can be used for key scan lines 0 to 9. Table 9-5 summarizes the alternate functions of Port 7. • Table 9-5 Alternate Functions of Port 7 Port 7 Pin Altern. Function P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P7.8 P7.9 Keyscan of line 0 Keyscan of line 1 Keyscan of line 2 Keyscan of line 3 Keyscan of line 4 Keyscan of line 5 Keyscan of line 6 Keyscan of line 7 Keyscan of line 8 Keyscan of line 9 Alternate Function Port 6 a) P7.9 P7.8 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 KEYSCAN9 KEYSCAN8 KEYSCAN7 KEYSCAN6 KEYSCAN5 KEYSCAN4 KEYSCAN3 KEYSCAN2 KEYSCAN1 KEYSCAN0 General Purpose Input/Output Figure 9-11 Port 7 I/O and Alternate Functions Data Sheet 155 2003-03-31 INCA-D PSB 21473 Dedicated Pins 10 Dedicated Pins Most of the input/output or control signals of the functional the INCA-D are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the USB interface, the IOM-2 interface, the oscillator, special control signals and the power supply. Table 10-1 summarizes the dedicated pins of the INCA-D. Table 10-1 Dedicated Pins Pin(s) Function VREF Reference Voltage BGREF Bandgap Reference Voltage MIP1/MIN1 Differential Mircrophone 1 Inputs MIP2/MIN2 Differential Mircrophone 2 Inputs MIP3/MIN3 Differential Mircrophone 3Inputs HOP1/HON1 Differential earpiece 1 Outputs HOP2/HON2 Differential earpiece 2 Output LSP/LSN Differential Loudspeaker Outputs ALE Address Latch Enable RD External Read Strobe WR/WRL External Write/Write Low Strobe LlA Line Interface LlB Line Interface NMI Non-Maskable Interrupt Input RSTIN Reset Input RSTOUT Reset Output XTAL1, XTAL2 Oscillator Input/Output DMNS, DPLS USB DU, DD, DCL, FSC IOM-2 interface BCL IOM-2 bit clock BRKIN, BRKOUT OCDS Break In, Break out TDI, TDO, TCK, TMS, TRST JTAG Interface TEST Test Mode Enable (JTAG) VDD, VSS Power Supply and Ground (10 pins each) Data Sheet 156 2003-03-31 INCA-D PSB 21473 Dedicated Pins The Reference Voltage VREF can be used for biasing external components. The DC voltage at VREF is the same as at the analog in-/output pins of the analog front-end (if enabled). The Bandgap Reference Voltage BGREF (1.2 V) is used for internal references. The pin BGREF is necessary to connect a filter capacitor (approx. 22nF), which forms a RCfilter together with an on-chip resistor of about 300kΩ. Symmetrical differential Microphone Inputs1,2 and 3 MIN1/MIN2/MIN3 and MIP1/MIP2/ MIP3. Differential Handset earpiece output for 200 Ω transducers HOPx/HONx Differential Loudspeaker output for 20 Ω loudspeaker LSP/LSN The Address Latch Enable signal ALE controls external address latches that provide a stable address in multiplexed bus modes. ALE is activated for every external bus cycle independent of the selected bus mode, ie. it is also activated for bus cycles with a demultiplexed address bus. ALE is not activated for internal accesses, ie. the internal RAM and the special function registers. The External Read Strobe RD controls the output drivers of external memory or peripherals when the INCA-D reads data from these external devices. During reset an internal pullup ensures an inactive (high) level on the RD output. The External Write Strobe WR/WRL controls the data transfer from the INCA-D to an external memory or peripheral device. This pin may either provide an general WR signal activated for both byte and word write accesses, or specifically control the low byte of an external 16-bit device (WRL) together with the signal WRH (alternate function of P3.12/ BHE). During reset an internal pullup ensures an inactive (high) level on the WR/WRL output. Note: Whether RD and WR/WRL remain idle during X-peripheral accesses depends on the value of bit VISIBLE of register SYSCON. The line interface consists of the two lines Lla and Llb. The IOM2-Interface consists of the four lines DCL, FSC, DD, and DU. DCL is the 1.536MHz bit-clock (double-bit clock). FSC the 8kHz frame synchronization signal. DD and DU serve as serial data out-/input, they require external pull-up resistors. The double bit-clock at pin DCL can always be output as single-bit-clock (divided by 2) at pin BCL. The JTAG and OCDS Interface offers an IEEE1149.1 compliant JTAG interface consisting of the lines TCK, TDI, TDO, TMS, TRST. The JTAG TAP controller allows to use the JTAG interface for purposes of on-chip debugging. In this OCDS mode, additional lines BRKIN and BRKOUT are provided for controlling the behaviour of the CPU. The pin TEST is part of the JTAG interface and required for production test of the INCA-D. If unused, all pins of the JTAG/OCDS interface can remain unconnected. Data Sheet 157 2003-03-31 INCA-D PSB 21473 Dedicated Pins The Non-Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal (eg. a power-fail signal). The NMI pin is sampled with every CPU clock cycle to detect transitions. The Oscillator Input XTAL1 and Output XTAL2 connect the internal Pierce oscillator to the external crystal. An external clock signal may be fed to the input XTAL1, leaving XTAL2 open. The Universal Serial Bus (USB) interface consists of the two lines DMNS and DPLS. Events inside the On Chip Debugging Interface (OCDS) can be triggered by BRKIN. One of the possible actions after event detection is setting pin BRKOUT. The Reset Input RSTIN allows to put the INCA-D into the well defined reset condition either at power-up or external events like a hardware failure or manual reset. The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input. The Reset Output RSTOUT provides a special reset signal for external circuitry. RSTOUT is activated at the beginning of the reset sequence, triggered via RSTIN, a watchdog timer overflow or by the SRST instruction. RSTOUT remains active (low) until the EINIT instruction is executed. This allows to initialize the controller before the external circuitry is activated. The Power Supply pins provide the power supply for the digital logic of the INCA-D. The respective VCC/VSS pairs should be decoupled as close to the pins as possible. For best results it is recommended to implement two-level decoupling, eg. (the widely used) 100 nF in parallel with 30...40 pF capacitors which deliver the peak currents. Note: All VDD pins and all VSS pins must be connected to the power supply and ground, respectively. Data Sheet 158 2003-03-31 INCA-D PSB 21473 The External Bus Interface 11 The External Bus Interface The external bus interface allows to access external peripherals and additional volatile and non-volatile memory. The external bus interface provides a number of configurations, so it can be taylored to fit perfectly into a given application system. Ports & Direction Control Alternate Functions Address Registers Mode Registers P0L / P0H BUSCON0 SYSCON RP0H P1L / P1H ADDRSEL1 BUSCON1 DP3 ADDRSEL2 BUSCON2 P3 ADDRSEL3 BUSCON3 P4 ADDRSEL4 BUSCON4 ODP6 DP6 P6 P0L/P0H P1L/P1H DP3 P3 P4 ODP6 DP6 P6 Control Registers RSTIN ALE RD WR/WRL BHE/WRH PORT0 Data Registers PORT1 Data Registers Port 3 Direction Control Register Port 3 Data Register Port 4 Data Register Port 6 Open Drain Control Register Port 6 Direction Control Register Port 6 Data Register ADDRSELx BUSCONx SYSCON RP0H Address Range Select Register 1...4 Bus Mode Control Register 0...4 System Control Register Port P0H Reset Configuration Register Control Registers Figure 11-1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller (EBC). The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers. The BUSCONx registers specify the external bus cycles in terms of address (mux/demux), data (16-bit/8-bit), chip selects and length (waitstates/ ALE / RW delay). These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx. The four pairs BUSCON1/ADDRSEL1...BUSCON4/ADDRSEL4 allow to define four independent “address windows”, while all external accesses outside these windows are controlled via register BUSCON0. Data Sheet 159 2003-03-31 INCA-D PSB 21473 The External Bus Interface 11.1 External Bus Modes When the external bus interface is enabled (bit BUSACTx=’1’) and configured (bitfield BTYP), the INCA-D uses a subset of its port lines together with some control lines to build the external bus. BTYP Encoding External Data Bus Width External Address Bus Mode 00 8-bit Data Demultiplexed Addresses 01 8-bit Data Multiplexed Addresses 10 16-bit Data Demultiplexed Addresses 11 16-bit Data Multiplexed Addresses The bus configuration (BTYP) for the address windows (BUSCON4...BUSCON1) is selected via software typically during the initialization of the system. The bus configuration (BTYP) for the default address range (BUSCON0) is selected via PORT0 during reset, otherwise BUSCON0 may be programmed via software just like the other BUSCON registers. The address space of the INCA-D is divided into segments of 64 KByte each. The 16-bit intra-segment address is output on PORT0 for multiplexed bus modes or on PORT1 for demultiplexed bus modes. When segmentation is disabled, only one 64 KByte segment is available. Because of the occupied 8 KBytes of memory in segment 0, only 56 can be used and accessed. Otherwise additional address lines may be output on Port 4, and/or several chip select lines may be used to select different memory banks or peripherals. These functions are selected during reset via bitfields SALSEL and CSSEL of register RP0H, respectively. Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during interrupt entry (segmentation active) or not (segmentation disabled). Multiplexed Bus Modes In the multiplexed bus modes the 16-bit intra-segment address as well as the data use PORT0. The address is time-multiplexed with the data and has to be latched externally. The width of the required latch depends on the selected data bus width, ie. an 8-bit data bus requires a byte latch (the address bits A15...A8 on P0H do not change, while P0L multiplexes address and data), a 16-bit data bus requires a word latch (the least significant address line A0 is not relevant for word accesses). The upper address lines (A21...A16) are permanently output on Port 4 (if segmentation is enabled) and do not require latches. The EBC initiates an external access by generating the Address Latch Enable signal (ALE) and then placing an address on the bus. The falling edge of ALE triggers an external latch to capture the address. After a period of time during which the address Data Sheet 160 2003-03-31 INCA-D PSB 21473 The External Bus Interface must have been latched externally, the address is removed from the bus. The EBC now activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the bus either by the EBC (for write cycles) or by the external memory/peripheral (for read cycles). After a period of time, which is determined by the access time of the memory/ peripheral, data become valid. Read cycles: Input data is latched and the command signal is now deactivated. This causes the accessed device to remove its data from the bus which is then tri-stated again. Write cycles: The command signal is now deactivated. The data remain valid on the bus until the next external bus cycle is started. Figure 11-2 Multiplexed Bus Cycle The bus cycle is described in number of TCL’s, where fCPU = 1/(2 TCL). Demultiplexed Bus Modes In the demultiplexed bus modes the 16-bit intra-segment address is permanently output on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data). The upper address lines are permanently output on Port 4 (if selected via SALSEL during reset). No address latches are required. The EBC initiates an external access by placing an address on the address bus. After a programmable period of time the EBC activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the data bus either by the EBC (for write cycles) Data Sheet 161 2003-03-31 INCA-D PSB 21473 The External Bus Interface or by the external memory/peripheral (for read cycles). After a period of time, which is determined by the access time of the memory/peripheral, data become valid. Read cycles: Input data is latched and the command signal is now deactivated. This causes the accessed device to remove its data from the data bus which is then tri-stated again. Write cycles: The command signal is now deactivated. If a subsequent external bus cycle is required, the EBC places the respective address on the address bus. The data remain valid on the bus until the next external bus cycle is started. Figure 11-3 Demultiplexed Bus Cycle The bus cycle is described in number of TCL’s, where fCPU = 1/(2 TCL). Switching between the Bus Modes The EBC allows to switch between different bus modes dynamically, ie. subsequent external bus cycles may be executed in different ways. Certain address areas may use multiplexed or demultiplexed buses or predefined waitstates. A change of the external bus characteristics can be initiated in two different ways: Reprogramming the BUSCON and/or ADDRSEL registers allows to either change the bus mode for a given address window, or change the size of an address window that uses a certain bus mode. Reprogramming allows to use a great number of different Data Sheet 162 2003-03-31 INCA-D PSB 21473 The External Bus Interface address windows (more than BUSCONs are available) on the expense of the overhead for changing the registers and keeping appropriate tables. Switching between predefined address windows automatically selects the bus mode that is associated with the respective window. Predefined address windows allow to use different bus modes without any overhead, but restrict their number to the number of BUSCONs. However, as BUSCON0 controls all address areas, which are not covered by the other BUSCONs, this allows to have gaps between these windows, which use the bus mode of BUSCON0. PORT1 will output the intra-segment address, when any of the BUSCON registers selects a demultiplexed bus mode, even if the current bus cycle uses a multiplexed bus mode. This allows to have an external address decoder connected to PORT1 only, while using it for all kinds of bus cycles. Note: Never change the configuration for an address area that currently supplies the instruction stream. Due to the internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration. Only change the configuration for address areas that are not currently accessed. This applies to BUSCON registers as well as to ADDRSEL registers. The usage of the BUSCON/ADDRSEL registers is controlled via the issued addresses. When an access (code fetch or data) is initiated, the respective generated physical address defines, if the access is made internally, uses one of the address windows defined by ADDRSEL4...1, or uses the default configuration in BUSCON0. After initializing the active registers, they are selected and evaluated automatically by interpreting the physical address. No additional switching or selecting is necessary during run time, except when more than the four address windows plus the default is to be used. Switching from demultiplexed to multiplexed bus mode represents a special case. The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1 as usual, if another BUSCON register selects a demultiplexed bus. However, in the multiplexed bus modes the address is also required on PORT0. In this special case the address on PORT0 is delayed by one CPU clock cycle, which delays the complete (multiplexed) bus cycle and extends the corresponding ALE signal (see figure below). This extra time is required to allow the previously selected device (via demultiplexed bus) to release the data bus, which would be available in a demultiplexed bus cycle. Data Sheet 163 2003-03-31 INCA-D PSB 21473 The External Bus Interface • Figure 11-4 Switching from Demultiplexed to Multiplexed Bus Mode The bus cycle is described in number of TCL’s, where fCPU = 1/(2 TCL). External Data Bus Width The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This saves on address latches, bus transceivers, bus routing and memory cost on the expense of transfer time. The EBC can control word accesses on an 8-bit data bus as well as byte accesses on a 16-bit data bus. Word accesses on an 8-bit data bus are automatically split into two subsequent byte accesses, where the low byte is accessed first, then the high byte. The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer. Byte accesses on a 16-bit data bus require that the upper and lower half of the memory can be accessed individually. In this case the upper byte is selected with the BHE signal, while the lower byte is selected with the A0 signal. So the two bytes of the memory can be enabled independent from each other, or together when accessing words. When writing bytes to an external 16-bit device, which has a single CS input, but two WR enable inputs (for the two bytes), the EBC can directly generate these two write control signals. This saves the external combination of the WR signal with A0 or BHE. In this Data Sheet 164 2003-03-31 INCA-D PSB 21473 The External Bus Interface case pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The respective byte will be written on both data bus halfs. When reading bytes from an external 16-bit device, whole words may be read and the INCA-D automatically selects the byte to be input and discards the other. However, care must be taken when reading devices that change state when being read, like FIFOs, interrupt status registers, etc. In this case individual bytes should be selected using BHE and A0. Bus Mode Transfer Rate (Speed factor for byte/word/dword access) System Requirements Free I/O Lines 8-bit Multiplexed Very low ( 1.5 / 3 / 6 ) Low (8-bit latch, byte bus) P1H, P1L 8-bit Demultipl. Low (1/2/4) Very low (no latch, byte bus) P0H 16-bit Multiplexed High ( 1.5 / 1.5 / 3 ) High (16-bit latch, word bus) P1H, P1L 16-bit Demultipl. Very high (1/1/2) Low (no latch, word bus) --- Note: PORT1 gets available for general purpose I/O, when none of the BUSCON registers selects a demultiplexed bus mode. Disable/Enable Control for Pin BHE (BYTDIS) Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The function of the BHE pin is enabled, if the BYTDIS bit contains a '0'. Otherwise, it is disabled and the pin can be used as standard I/O pin. The BHE pin is implicitly used by the External Bus Controller to select one of two byte-organized memory chips, which are connected to the INCA-D via a word-wide external data bus. After reset the BHE function is automatically enabled (BYTDIS = '0'), if a 16-bit data bus is selected during reset, otherwise it is disabled (BYTDIS=’1’). It may be disabled, if byte access to 16-bit memory is not required, and the BHE signal is not used. Segment Address Generation During external accesses the EBC generates a (programmable) number of address lines on Port 4, which extend the 16-bit address output on PORT0 or PORT1, and so increase the accessible address space. The number of segment address lines is selected during reset and coded in bit field SALSEL in register RP0H (see table below and Table 24-3, “Code definitions of startup configurations,” on page 603). Table 11-1 Coding of SALSEL SALSEL Segment Address Lines Directly accessible Address Space 11 Two: A17...A16 256 KByte 10 Six: A21...A16 4 MByte (Maximum) Data Sheet 165 2003-03-31 INCA-D PSB 21473 The External Bus Interface Table 11-1 Coding of SALSEL SALSEL Segment Address Lines Directly accessible Address Space 01 None 64 KByte (Minimum) 00 Four: 1 MByte (default) A19...A16 Note: The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals. CS Signal Generation During external accesses the EBC can generate a (programmable) number of CS lines on Port 6, which allow to directly select external peripherals or memory banks without requiring an external decoder. The number of CS lines is selected during reset and coded in bits CSSEL in register RP0H (see table below and Table 24-3, “Code definitions of startup configurations,” on page 603). Table 11-2 CSSEL (P0H.2:1) Coding of CSSEL Chip Select Lines 11 Reserved 10 None pins P6.0 and P6.1usable as GP I/Os 01 CS1 and CS0 availabe two CS lines at pins P6.0 and P6.1 (default) 00 Reserved When CSSEL=01 has been selected, the chip select signal CS1 has to be enabled manually by activating the corresponding alternate function of port pin P6.1 (see Chapter 9.6.1). Otherwise only the chip select signal CS0 is enabled. The activation of CS0 (and the implicit selection of the alternate function of P6.0) is done automativcally by the External Bus Controller. The CSx outputs are associated with the BUSCONx registers and are driven active (low) for any access within the address area defined for the respective BUSCON register. For any access outside this defined address area the respective CSx signal will go inactive (high). At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated. All other CS lines are deactivated (driven high) at the same time. Note: The CSx signals will not be updated for an access to any internal address area (ie. when no external bus cycle is started), even if this area is covered by the respective ADDRSELx register. An access to an on-chip X-Peripheral deactivates all external CS signals. Data Sheet 166 2003-03-31 INCA-D PSB 21473 The External Bus Interface Upon accesses to address windows without a selected CS line all selected CS lines are deactivated. The chip select signals allow to be operated in four different modes, which are selected via bits CSWENx and CSRENx in the respective BUSCONx register. CSWENx CSRENx Chip Select Mode 0 0 Address Chip Select (Default after Reset, mode for CS0) 0 1 Read Chip Select 1 0 Write Chip Select 1 1 Read/Write Chip Select Address Chip Select signals remain active until an access to another address window. An address chip select becomes active with the falling edge of ALE and becomes inactive with the falling edge of ALE of an external bus cycle that accesses a different address area. No spikes will be generated on the chip select lines. Read or Write Chip Select signals remain active only as long as the associated control signal (RD or WR) is active. This also includes the programmable read/write delay. Read chip select is only activated for read cycles, write chip select is only activated for write cycles, read/write chip select is activated for both read and write cycles (write cycles are assumed, if any of the signals WRH or WRL gets active). These modes save external glue logic, when accessing external devices like latches or drivers that only provide a single enable input. Note: CS0 provides an address chip select directly after reset when the first instruction is fetched. Segment Address versus Chip Select The external bus interface of the INCA-D supports many configurations for the external memory. By increasing the number of segment address lines the INCA-D can address a linear address space of 256 KByte, 1 MByte or 4 MByte. This allows to implement a large sequential memory area, and also allows to access a great number of external devices, using an external decoder. By increasing the number of CS lines the INCA-D can access memory banks or peripherals without external glue logic. These two features may be combined to optimize the overall system performance. Enabling 4 segment address lines and 2 chip select lines eg. allows to access two memory banks of 1 MByte each. So the available address space is 2 MByte (without glue logic). Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during interrupt entry (segmentation active) or not (segmentation disabled). Data Sheet 167 2003-03-31 INCA-D PSB 21473 The External Bus Interface 11.2 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory configurations with different types of memories and/or peripherals. The following parameters of an external bus cycle are programmable: • ALE Control defines the ALE signal length and the address hold time after its falling edge • Memory Cycle Time (extendable with 1...15 waitstates) defines the allowable access time • Memory Tri-State Time (extendable with 1 waitstate) defines the time for a data driver to float • Read/Write Delay Time defines when a command is activated after the falling edge of ALE Note: Internal accesses are executed with maximum speed and therefore are not programmable. External acceses use the slowest possible bus cycle after reset. The bus cycle timing may then be optimized by the initialization software. ALECTL MCTC MTTC Figure 11-5 Programmable External Bus Cycle Data Sheet 168 2003-03-31 INCA-D PSB 21473 The External Bus Interface ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to ‘1’, external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock. Also the address hold time after the falling edge of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer within a bus cycle refers to the same CLKOUT edges as usual (ie. the data transfer is delayed by one CPU clock). This allows more time for the address to be latched. Note: ALECTL0 is ‘1’ after reset to select the slowest possible bus cycle, the other ALECTLx are ‘0’ after reset. Figure 11-6 ALE Length Control Programmable Memory Cycle Time The INCA-D allows the user to adjust the controller's external bus cycles to the access time of the respective memory or peripheral. This access time is the total time required Data Sheet 169 2003-03-31 INCA-D PSB 21473 The External Bus Interface to move the data to the destination. It represents the period of time during which the controller’s signals do not change. Figure 11-7 Memory Cycle Time The external bus cycles of the INCA-D can be extended for a memory or peripheral, which cannot keep pace with the controller’s maximum speed, by introducing wait states during the access (see figure above). During these memory cycle time wait states, the CPU is idle, if this access is required for the execution of the current instruction. The memory cycle time wait states can be programmed in increments of one CPU clock within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON registers. 15- waitstates will be inserted. Programmable Memory Tri-State Time The INCA-D allows the user to adjust the time between two subsequent external accesses to account for the tri-state time of the external device. The tri-state time defines, when the external device has released the bus after deactivation of the read command (RD). Data Sheet 170 2003-03-31 INCA-D PSB 21473 The External Bus Interface Figure 11-8 Memory Tri-State Time The output of the next address on the external bus can be delayed for a memory or peripheral, which needs more time to switch off its bus drivers, by introducing a wait state after the previous bus cycle (see figure above). During this memory tri-state time wait state, the CPU is not idle, so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle. The memory tri-state time waitstate requires one CPU clock (28 ns at fCPU = 36 MHz) and is controlled via the MTTCx bits of the BUSCON registers. A waitstate will be inserted, if bit MTTCx is ‘0’ (default after reset). Note: External bus cycles in multiplexed bus modes implicitly add one tri-state time waitstate in addition to the programmable MTTC waitstate. Read/Write Signal Delay The INCA-D allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals. The read/write delay controls the time between the falling edge of ALE and the falling edge of the command. Without read/ write delay the falling edges of ALE and command(s) are coincident (except for propagation delays). With the delay enabled, the command(s) become active half a CPU clock after the falling edge of ALE. The read/write delay does not extend the memory cycle time, and does not slow down the controller in general. In multiplexed bus modes, however, the data drivers of an external device may conflict with the INCA-D’s address, when the early RD signal is used. Therefore multiplexed bus cycles should always be programmed with read/write delay. Data Sheet 171 2003-03-31 INCA-D PSB 21473 The External Bus Interface 1) The data drivers from the previous bus cycle should be disabled when the RD signal becomes active. Figure 11-9 Read/Write Delay The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The command(s) will be delayed, if bit RWDCx is ‘0’ (default after reset). 11.3 Controlling the External Bus Controller A set of registers controls the functions of the EBC. General features like the usage of interface pins (WR, BHE) and segmentation are controlled via register SYSCON. The properties of a bus cycle like chip select mode, length of ALE, external bus mode, read/ write delay and waitstates are controlled via registers BUSCON4...BUSCON0. Four of these registers (BUSCON4...BUSCON1) have an address select register (ADDRSEL4...ADDRSEL1) associated with them, which allows to specify up to four address areas and the individual bus characteristics within these areas. All accesses that are not covered by these four areas are then controlled via BUSCON0. Data Sheet 172 2003-03-31 INCA-D PSB 21473 The External Bus Interface This allows to use memory components or peripherals with different interfaces within the same system, while optimizing accesses to each of them. SYSCON (FF12H / 89H) 15 14 13 STKSZ rw SFR-b 12 11 10 9 8 0 SGT DIS 0 BYT DIS CLK EN r rw r rw rw 7 Reset Value: EA84H 6 WR CS CFG CFG rw rw 5 4 3 0 0 0 r r r 2 1 0 VISI 0 rw r XPEN BLE rw Bit Function VISIBLE Visible Mode Control 0: Accesses to XBUS peripherals are done internally 1: XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0: Accesses to the on-chip X-Peripherals and their functions are disabled 1: The on-chip X-Peripherals are enabled and can be accessed CSCFG Chip Select Configuration Control 0: Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins synchronously. 1: Unlatched CS mode. The CS signals are directly derived from the address and driven to the (enabled) port pins. WRCFG Write Configuration Control (Set according to pin P0H.0 during reset) 0: Pins WR and BHE retain their normal function 1: Pin WR acts as WRL, pin BHE acts as WRH CLKEN System Clock Output Enable (CLKOUT 1)) 0: 1: CLKOUT disabled CLKOUT enabled; BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width) 0: Pin BHE enabled 1: Pin BHE disabled, pin may be used for general purpose I/O SGTDIS Segmentation Disable/Enable Control ‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit) ‘1’: Segmentation disabled (Only IP is saved/restored) STKSZ System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words 1) The implemented pad type for CLKOUT supports only an open-drain output driver Note: Register SYSCON cannot be changed after execution of the EINIT instruction. Note: Only exception: bit VISIBLE can also be changed by the on-chip debug support with DPEC access. Data Sheet 173 2003-03-31 INCA-D PSB 21473 The External Bus Interface The layout of the five BUSCON registers is identical. Registers BUSCON4...BUSCON1, which control the selected address windows, are completely under software control, while register BUSCON0, which eg. is also used for the very first code access after reset, is partly controlled by hardware, ie. it is initialized via PORT0 during the reset sequence. This hardware control allows to define an appropriate external bus for systems, where no internal program memory is provided. BUSCON0 (FF0CH / 86H) 15 14 CSW CSR EN0 EN0 rw rw SFR 13 12 11 0 0 0 rw r r r 10 9 BUS ALE ACT0 CTL0 rw rw 8 14 CSW CSR EN1 EN1 rw rw 14 CSW CSR EN2 EN2 rw rw r rw 14 CSW CSR EN3 EN3 rw rw 13 12 11 0 0 0 rw r r r 10 9 BUS ALE ACT1 CTL1 rw rw 8 14 CSW CSR EN4 EN4 rw rw 4 12 11 0 0 0 rw - r - 10 9 BUS ALE ACT2 CTL2 rw rw 6 BTYP r rw 5 4 12 11 0 0 0 rw r r r 10 9 BUS ALE ACT3 CTL3 rw rw rw 12 11 0 0 0 rw r r r 10 9 6 0 BTYP - rw 5 BUS ALE ACT4 CTL4 rw rw 2 1 0 MCTC rw 4 3 MTT RWD C2 C2 rw 2 1 0 MCTC rw rw Reset Value: 0000H 7 6 0 BTYP r rw 8 3 rw 5 4 3 MTT RWD C3 C3 rw 2 1 0 MCTC rw SFR 13 rw Reset Value: 0000H 7 8 0 MCTC MTT RWD C1 C1 SFR 13 1 Reset Value: 0000H 7 8 2 rw SFR 13 3 MTT RWD C0 C0 rw 0 BUSCON4 (FF1AH / 8DH) 15 5 SFR BUSCON3 (FF18H / 8CH) 15 6 BTYP BUSCON2 (FF16H / 8BH) 15 7 0 BUSCON1 (FF14H / 8AH) 15 Reset Value: 0680H rw Reset Value: 0000H 7 6 0 BTYP r rw 5 4 MTT RWD C4 C4 rw rw 3 2 1 0 MCTC rw Note: As default the bits BUSACT0 and ALECTL0 are set (‘1’) and bit field BTYP is loaded with the bus configuration selected via PORT0. Data Sheet 174 2003-03-31 INCA-D PSB 21473 The External Bus Interface Bit Function MCTC Memory Cycle Time Control (Number of memory cycle time wait states) 0 0 0 0 : 15 waitstates (Number = 15 - ) ... 1 1 1 1 : No waitstates RWDCx Read/Write Delay Control for BUSCONx ‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE ‘1’: No read/write delay: activate command with falling edge of ALE MTTCx Memory Tristate Time Control ‘0’: 1 waitstate ‘1’: No waitstate BTYP External Bus Configuration 0 0 : 8-bit Demultiplexed Bus 0 1 : 8-bit Multiplexed Bus 1 0 : 16-bit DemultiplexedBus 1 1 : 16-bit Multiplexed Bus Note: For BUSCON0 BTYP is defined via PORT0 during reset. ALECTLx ALE Lengthening Control ‘0’: Normal ALE signal ‘1’: Lengthened ALE signal BUSACTx Bus Active Control ‘0’: External bus disabled ‘1’: External bus enabled (within the respective address window, see ADDRSEL) CSRENx Read Chip Select Enable ‘0’: The CS signal is independent of the read command (RD) ‘1’: The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable ‘0’: The CS signal is independent of the write command (WR,WRL,WRH) ‘1’: The CS signal is generated for the duration of the write command Data Sheet 175 2003-03-31 INCA-D PSB 21473 The External Bus Interface ADDRSEL1 (FE18H / 0CH) 15 14 13 12 11 SFR 10 9 8 14 13 12 11 14 13 12 11 14 Bit 13 12 11 5 4 3 2 1 rw rw SFR 10 9 8 7 6 5 4 3 2 1 RGSZ rw rw SFR 10 9 8 7 6 5 4 3 2 1 RGSZ rw rw SFR 9 8 0 Reset Value: 0000H RGSAD 10 0 Reset Value: 0000H RGSAD ADDRSEL4 (FE1EH / 0FH) 15 6 RGSZ ADDRSEL3(FE1CH / 0EH) 15 7 RGSAD ADDRSEL2 (FE1AH / 0DH) 15 Reset Value: 0000H 0 Reset Value: 0000H 7 6 5 4 3 2 1 RGSAD RGSZ rw rw 0 Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONx/ ADDRSELx register pair. See table below. RGSAD Range Start Address Defines the upper bits of the start address (A23..A12) of the internal addressable address space. Only address lines A21..A0 can be accessed externally. The possible start addresses for A21..A12 are summarized in the table below. Note: The 2 chip selects can be used to select a memory window of 4 MByte each. In this case the RGSAD bit 14 has to programmed accordingly. Note: There is no register ADDRSEL0, as register BUSCON0 controls all external accesses outside the four address windows of BUSCON4...BUSCON1 within the complete address space. Data Sheet 176 2003-03-31 INCA-D PSB 21473 The External Bus Interface Definition of Address Areas The four register pairs BUSCON4/ADDRSEL4...BUSCON1/ADDRSEL1 allow to define 4 separate address areas within the address space of the INCA-D. Within each of these address areas external accesses can be controlled by one of the four different bus modes, independent of each other and of the bus mode specified in register BUSCON0. Each ADDRSELx register in a way cuts out an address window, within which the parameters in register BUSCONx are used to control external accesses. The range start address of such a window defines the upper address bits, which are not used within the address window of the specified size (see table below). For a given window size only those upper address bits of the start address are used (marked “R”), which are not implicitly used for addresses inside the window. The lower bits of the start address (marked “x”) are disregarded. Bit field RGSZ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx Resulting Window Size Relevant Bits (R) of Start Address (A21...A12) 4 KByte 8 KByte 16 KByte 32 KByte 64 KByte 128 KByte 256 KByte 512 KByte 1 MByte 2 MByte 4 MByte Reserved Reserved. R R R R R R R R R R x R R R R R R R R R x x R R R R R R R R x x x R R R R R R R x x x x R R R R R R x x x x x R R R R R x x x x x x R R R R x x x x x x x R R R x x x x x x x x R R x x x x x x x x x R x x x x x x x x x x Address Window Arbitration For each access the EBC compares the current address with all address select registers ( ADDRSELx and XADRSx). This comparison is done in four levels. Priority 1: The XADRSx registers are evaluated first. A match with one of these registers directs the access to the respective X-Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers. Priority 2: Registers ADDRSEL2 and ADDRSEL4 are evaluated before ADDRSEL1 and ADDRSEL3, respectively. A match with one of these registers directs the access to the respective external area using the corresponding BUSCONx register and ignoring registers ADDRSEL1/3 (see figure below). Priority 3: A match with registers ADDRSEL1 or ADDRSEL3 directs the access to the respective external area using the corresponding XBCONx register. Data Sheet 177 2003-03-31 INCA-D PSB 21473 The External Bus Interface Priority 4: If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCON0. • XBCON0 BUSCON2 BUSCON4 BUSCON1 BUSCON3 Active Window Inactive Window BUSCON0 Figure 11-10 Address Window Arbitration Note: Only the indicated overlaps are defined. All other overlaps lead to erroneous bus cycles. Eg. ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1. The hardwired XADRSx registers are defined non-overlapping. For a description of the regsiter RP0H which holds the reset configuration (number of chip select lines, address range etc.) please refer to chapter “System Startup Configuration” on page 600. Precautions and Hints • The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set. • PORT1 will output the intra-segment address as long as at least one of the BUSCON registers selects a demultiplexed external bus, even for multiplexed bus cycles. • Not all address areas defined via registers ADDRSELx may overlap each other. The operation of the EBC will be unpredictable in such a case. See chapter „Address Window Arbitration“. • The address areas defined via registers ADDRSELx may overlap internal address areas. Internal accesses will be executed in this case. • For any access to an internal address area the EBC will remain inactive (see EBC Idle State). 11.4 EBC Idle State When the external bus interface is enabled, but no external access is currently executed, the EBC is idle. As long as only internal resources (from an architecture point of view) like IRAM, GPRs or SFRs, etc. are used the external bus interface does not change (see table below). Data Sheet 178 2003-03-31 INCA-D PSB 21473 The External Bus Interface Accesses to on-chip X-Peripherals are also controlled by the EBC. However, even though an X-Peripheral appears like an external peripheral to the controller, the respective accesses do not generate valid external bus cycles. Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface (see table below). The „address“ mentioned above includes PORT1, Port 4, BHE and ALE which also pulses for an XBUS cycle. The external CS signals on Port 6 are driven inactive (high) because the EBC switches to an internal XCS signal. The external control signals (RD and WR or WRL/WRH if enabled) don’t remain inactive during BUS accesses. When internal XRAM addresses are accessed, the control signals show the same behavior as for external accesses. Table 11-3 Status of the external bus interface during EBC idle state: Pins Internal accesses only XBUS accesses PORT0 Tristated (floating) Tristated (floating) for read accesses XBUS write data for write accesses PORT1 Last used external address (if used for the bus interface) Last used XBUS address (if used for the bus interface) Port 4 Last used external segment address (on selected pins) Last used XBUS segment address (on selected pins) Port 6 Active external CS signal corresponding to last used address Inactive (high) for selected CS signals BHE Level corresponding to last external access Level corresponding to last XBUS access ALE Inactive (low) Pulses as defined for X-Peripheral RD Inactive (high) Level corresponding to last XBUS access WR/WRL Inactive (high) Level corresponding to last XBUS access WRH Inactive (high) Level corresponding to last XBUS access Data Sheet 179 2003-03-31 INCA-D PSB 21473 The Watchdog Timer (WDT) 12 The Watchdog Timer (WDT) To allow recovery from software or hardware failure, the INCA-D provides a Watchdog Timer. If the software fails to service this timer before an overflow occurs, an internal reset sequence will be initiated. This internal reset will also pull the RSTOUT pin low, which also resets the peripheral hardware, which might be the cause for the malfunction. When the watchdog timer is enabled and the software has been designed to service it regularly before it overflows, the watchdog timer will supervise the program execution, as it only will overflow if the program does not progress properly. The watchdog timer will also time out, if a software error was due to hardware related failures. This prevents the controller from malfunctioning for longer than a user-specified time. The watchdog timer provides two registers: a read-only timer register that contains the current count, and a control register for initialization. Reset Indication Pin RSTOUT Data Registers Control Registers WDT WDTCON Figure 12-1 SFRs and Port Pins associated with the Watchdog Timer The watchdog timer is a 16-bit up counter which can be clocked with the CPU clock (fCPU) either divided by 2 or divided by 128. This 16-bit timer is realized as two concatenated 8-bit timers (see figure below). The upper 8 bits of the watchdog timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits are reset on each service access. Figure 12-2 Watchdog Timer Block Diagram Data Sheet 180 2003-03-31 INCA-D PSB 21473 The Watchdog Timer (WDT) 12.1 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON. This register specifies the reload value for the high byte of the timer, selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow. WDTCON (FFAEH / D7H) 15 14 13 12 11 SFR-b 10 9 8 Reset Value: 003CH 7 6 5 WDTREL 0 0 1 rw r r r 4 3 LHW SHW R R r r 2 SW R r 1 0 WDT WDT R IN r rw The reset value depends on the Reset Source. Bit Function WDTIN Watchdog Timer Input Frequency Selection ‘0’: Input frequency is fCPU / 2 ‘1’: Input frequency is fCPU / 128 WDTR1) Watchdog Timer Reset Indication Flag Set by the watchdog timer on an overflow. Cleared by the SRVWDT instruction. SWR Software Reset Set by the command SRST SHWR Short Hardware Reset Set by the Input RSTIN LHWR Long Hardware Reset Set by the Input RSTIN or by Undervoltage Detection WDTREL Watchdog Timer Reload Value (for the high byte of WDT) 1) More than one reset source may be visible. After EINIT all reset bits are cleared After any software reset, external hardware reset (see note), or watchdog timer reset, the watchdog timer is enabled and starts counting up from 0000H with the frequency fCPU/ 2. The input frequency may be switched to fCPU/128 by setting bit WDTIN. The watchdog timer can be disabled via the instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT (End of Initialization) or the SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions disables the execution of DISWDT. Data Sheet 181 2003-03-31 INCA-D PSB 21473 The Watchdog Timer (WDT) When the watchdog timer is not disabled via instruction DISWDT, it will continue counting up, even during Idle Mode. If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFH the watchdog timer will overflow and cause an internal reset. This reset will pull the external reset indication pin RSTOUT low. It differs from a software or external hardware reset in that bit WDTR (Watchdog Timer Reset Indication Flag) of register WDTCON will be set. A hardware reset or the SRVWDT instruction will clear this bit. Bit WDTR can be examined by software in order to determine the cause of the reset. A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled. To prevent the watchdog timer from overflowing, it must be serviced periodically by the user software. The watchdog timer is serviced with the instruction SRVWDT, which is a protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON. Servicing the watchdog timer will also reset bit WDTR. After being serviced the watchdog timer continues counting up from the value ( * 28). Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer (eg. by fetching and executing a bit pattern from a wrong location) is minimized. When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered, rather than the instruction be executed. The time period for an overflow of the watchdog timer is programmable in two ways: • the input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON to be either fCPU/2 or fCPU/128. • the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON. The period PWDT between servicing the watchdog timer and the next overflow can therefore be determined by the following formula: PWDT = 2(1 + *6) * (216 - * 28) fCPU Note: For safety reasons, the user is advised to rewrite WDTCON each time before the watchdog timer is serviced Data Sheet 182 2003-03-31 INCA-D PSB 21473 The Bootstrap Loader 13 The Bootstrap Loader The built-in bootstrap loader of the INCA-D provides a mechanism to load the startup program, which is executed after reset, via the serial interface. The bootstrap loader moves code/data into the internal RAM, but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine. It may be used to provide lookup tables or may provide “core-code”, ie. a set of general purpose subroutines, eg. for I/O operations, number crunching, system initialization, etc. The boot strap loader program resides inside the internal ROM. It is used to download an executable code into the internal memory via ASC. The ASC bootstrap loader is similar to the loader used in the C167 microprocessor family. However, there are some major differences: • The baudrate error is minimized because the reload value for the baudrate generator as well as the fractional divider (register S0FDV) are modified according to the measured time of the received zero byte. • The user program is started by a jump to its start address instead of a hardware or software reset. 13.1 Activation of ASC Bootstrap Loader The ASC bootstrap loader in ROM is activated by a hardware reset (pin RSTIN) under the following conditions: • Port 0.4 is pulled low by an external pull-down resistor. • Port 0.3 is left open. • Pin TEST is connected to VSS Data Sheet 183 2003-03-31 INCA-D PSB 21473 The Bootstrap Loader RSTIN P0L.4 1) 4) 2) RxD0 3) TxD0 5) CSP:IP 6) Int. Boot ROM BSL-routine 32 bytes user software 1) BSL initialization time, > 2µs @ fCPU = 20 MHz. Zero byte (1 start bit, eight ‘0’ data bits, 1 stop bit), sent by host. 3) Identification byte, sent by INCA-D. 4) 32 bytes of code / data, sent by host. 2) 5) 6) Caution: TxD0 is only driven a certain time after reception of the zero byte. Internal Boot ROM. Figure 13-1 Bootstrap Loader Sequence After reset, the microcontroller expects the serial reception of a zero byte (8 data bits = 00H, one stop bit, no parity) from a host at pin RXD (P3.11). The time is measured by timer T6, which runs at maximum speed. The result T6 depends on the baud rate BR and the CPU clock frequency fCPU. T6 = 9 * fCPU / (4*BR) (1) Factor 9 results from zero byte duration including start bit, factor 4 from T6 prescaler. Using T6, the bootstrap loader software calculates the optimum combination of • FDV = value of the Fractional Divider Register S0FDV • BG = Reload value for the Baud rate Timer / Reload Register S0BG For this purpose, the software modifies FDV in a loop and calculates BG. As described in Chapter 15, the baud rate is given by: BR = FDV * fCPU / (512*16*(BG+1)) (2) Thus, BG can be calculated from equation 1 and 2 in the following way: BG = (T6 * FDV * 4) / (9*512*16) - 1 = (T6 * FDV - 18432) / 18432 Data Sheet 184 (3) 2003-03-31 INCA-D PSB 21473 The Bootstrap Loader To get a rounded integer result, 18432/2 is added to numerator. So the software uses actually the following equation: BG = (T6 * FDV - 9216) / 18432 (4) The remainder of the division will be stored. The absolute error (in T6 units) introduced by this division is: Error0 = |T6 - T6(due to BG calculation)| (5) = |18432 * BG + Remainder + 9216) / FDV - 18432 * (BG + 1) / FDV| = |Remainder - 9216| / FDV To calculate the error with higher resolution and to get a rounded result, the numerator is shifted left 10 bits, and FDV/2 is added. So the software uses actually the following equation: Error= ((|Remainder - 9216| >1))/ FDV (6) The software searches for the combination of FDV and BG that produces the minimum error. FDV is modified only from 256 to 512, because values 1 to 255 would not produce better results. If the optimum FDV value is 512, it will be changed to 0 according to the ASC description. • • • • • Then the serial port is initialized in the following way: 8 data bits, one stop bit, no parity bit, fractional divider and baud rate generator enabled, calculated values for S0FDV and S0BG, TXD output set to 1 and enabled. An identification byte D5H is sent back to the host via pin TXD (P3.10). Note: The range of timer T6 (max. 65535 increments) determines the lowest possible baud rate: BR > (9 * fCPU) / (4* 65535) Note: At very high baud rates, the accuracy is limited by the restrictions for frequency division via S0FDV and S0BG. Additionally, the quantization error of timer T6 and signal distortion effects (e.g., different on/off delays) must be taken into account. 13.2 Loading the Startup Code At the next step, the ASC bootstrap loader goes into a loop expecting 32 bytes to be received. This loop does not have an exit on time-out condition, so the program will wait forever unless 32 bytes are received. The received bytes are stored sequentially in the internal RAM beginning at address 00’FA40H and ending at address 00’FA5FH. After the reception of the 32 bytes, the ASC bootstrap loader automatically performs a jump to location 00’FA40H, and the loaded program will be executed. Starting at this point, the program is no longer defined by the ROM code. Data Sheet 185 2003-03-31 INCA-D PSB 21473 The Bootstrap Loader In most cases 32 bytes are not sufficient for a complete loader program. Therefore this code will normally be used as a pre-loader to copy the main loader program to internal RAM with start address 00’FA60H. The maximum byte address of internal RAM is 00’FDFFH. After the reception of the main loader, the 32-byte pre-loader performs a jump to the start address of this program. 13.3 Transfer of User Program After the boot strap loader execution, the system has the configuration in table 13-1: Table 13-1 Register Content After Boot Strap Loader Execution Peripheral Unit State After Bootstrap Loader Execution Watchdog Timer disabled CP Register FA00H SYSCON Register 0E00H BUSCON0 Register 0XX0H according to bus configuration during reset XADRS1 Register 0DF0H XBCON1 Register 04BFH SP Register FA40H STKUN Register FA40H STKOV Register FA20H S0CON Register 8011H S0DV Register Depending on zero byte evaluation S0BG Register Reload value depending on zero byte evaluation S0TBIR in S0TBIC Register 1 TxD/P3.10 1 DP3.10 1 Note: During the entire bootstrap loading sequence, all interrupts and error resets must remain disabled. Note: The user program can not be started via a hardware or software reset. An address range from 00'0000H to 00'7FFFH (32 KByte) is reserved for internal accesses. Code fetches from this area will be made to the boot ROM. Data fetches from this area will return undefined values because there are no valid internal ROM data. The maximum stack size is 32 words. If necessary, the user program can modify the above configuration. Data Sheet 186 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit 14 General Purpose Timer Unit Data Registers Ports & Direction Control Alternative Functions Control Registers Interrupt Control ODP3 T2 T2CON T2IC DP3 T3 T3CON T3IC P3 T4 T4CON IRQ14_STA T2IN/P3.7 T2EUD/CAPIN/P3.2 T3OUT/P3.3 T3IN/P3.6 T4IN/P3.5 T5IN/P3.0 T3EUD/P3.4 T4EUD/P3.1 T5EUD/P3.9 T6EUD/P3.13 T6OUT/P3.1 T6IN/P3.8 ODP3 Port 3 Open Drain Control Register T2 GPT1 Timer 2 Register DP3 P3 T2CON T3CON Port 3 Direction Control Register Port 3 Data Register GPT1 Timer 2 Control Register GPT1 Timer 3 Control Register T3 T4 T2IC T3IC GPT1 Timer 3 Register GPT1 Timer 4 Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Interrupt Control Register T4CON GPT1 Timer 4 Control Register IQR14_STA Status register of combined interrupt COMB2INT Figure 14-1 SFR associated with GPT The General Purpose Timer Unit (GPT) represents very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. In the INCA-D, there are following alternate function pins available: T2IN, T2EUD/ CAPIN, T3IN, T3EUD, T3OUT, T4IN, T4EUD/T6OUT, T5IN, T5EUD, T6IN, and T6EUD. These pins are part of the alternate functions of Port 3; please refer to Table 9-2, “Alternate Functions of Port 3,” on page 144. The GPT incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. Block 1 contains 3 timers/counters with a maximum resolution of fTimer/4. The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer. Data Sheet 187 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Block 2 contains 2 timers/counters with a maximum resolution of fTimer/2. An additional CAPREL register supports capture and reload operation with extended functionality. The following enumeration summarizes all features to be supported: l Timer Block 1: – fTimer/4 maximum resolution. – 3 independent timers/counters. – Timers/counters can be concatenated. – 4 operating modes (timer, gated timer, counter, incremental). – Separate interrupt nodes. l Timer Block 2: – fTimer/2 maximum resolution. – 2 independent timers/counters. – Timers/counters can be concatenated. – 3 operating modes (timer, gated timer, counter). – Extended capture/reload functions via 16-bit Capture/Reload register CAPREL. – Separate interrupt nodes. 14.1 Functional Description of Timer Block 1 All three timers of block 1 (T2, T3, T4) can run in 4 basic modes, which are timer, gated timer, counter and incremental interface mode, and all timers can either count up or down. Each timer has an input line (TxIN) associated with it which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (Up / Down) may be programmed via software or may be dynamically altered by a signal at an external control input line. An overflow/underflow of core timer T3 is indicated by the output toggle latch T3OTL whose state may be output on related line T3OUT and on line T3OFL. The auxiliary timers T2 and T4 may additionally be concatenated with the core timer, or used as capture or reload registers for the core timer. Concatenation of T3 with other timers is provided through line T3OFL. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2, T3, or T4, which are located in the non-bitaddressable SFR space. When any of the timer registers is written to by the CPU in the state immediately before a timer increment, decrement, reload, or capture is to be performed, the CPU write operation has priority in order to guarantee correct results. Data Sheet 188 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit T3OFL Figure 14-2 Structure of Timer Block 1 14.1.1 Core Timer T3 The operation of the core timer T3 is controlled by its bitaddressable control register T3CON. Run Control The timer can be started or stopped by software through bit T3R (Timer T3 Run Bit). Setting bit T3R to ‘1’ will start the timer, clearing T3R stops the timer. In gated timer mode, the timer will only run if T3R = ‘1’ and the gate is active (high or low, as programmed). Note: When bit T2RC/T4RC in timer control register T2CON/T4CON is set to ’1’, T3R will also control (start and stop) auxiliary timer T2/T4. Data Sheet 189 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Count Direction Control The count direction of the core timer can be controlled either by software or by the external input line T3EUD (Timer T3 External Up/Down Control Input). These options are selected by bits T3UD and T3UDE in control register T3CON. When the up/down control is done by software (bit T3UDE = ‘0’), the count direction can be altered by setting or clearing bit T3UD. When T3UDE = ‘1’, line T3EUD is selected to be the controlling source of the count direction. However, bit T3UD can still be used to reverse the actual count direction, as shown in the table below. If T3UD = ‘0’ and line T3EUD shows a low level, the timer is counting up. With a high level at T3EUD the timer is counting down. If T3UD = ‘1’, a high level at line T3EUD specifies counting up, and a low level specifies counting down. The count direction can be changed regardless of whether the timer is running or not. When line T3EUD is used as external count direction control input, its associated port pin must be configured as input. Table 14-1 GPT1 Core Timer T3 Count Direction Control Line TxEUD Bit TxUDE Bit TxUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note: The direction control works the same for core timer T3 and for auxiliary timers T2 and T4. Therefore the lines and bits are named Tx... Timer 3 Overflow/Underflow Monitoring An overflow or underflow of timer T3 will clock the overflow toggle latch T3OTL in control register T3CON. T3OTL can also be set or reset by software. Bit T3OE (Overflow/ Underflow Output Enable) in register T3CON enables the state of T3OTL to be monitored via an external line T3OUT. If this line is configured as output, T3OTL can be used to control external HW. In addition, T3OTL can be used in conjunction with the timer over/underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4. For this purpose, the state of T3OTL does not have to be available at any port pin, because an internal connection is provided for this option. Data Sheet 190 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit An overflow or underflow of timer T3 can also be used to clock other timers. For this purpose, there is the special output line T3OFL. Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘000B’. In this mode, T3 is clocked with the module clock fTimer divided by a programmable prescaler, which is controlled by bit field T3I and bit FM1. The input frequency fT3 for timer T3 and its resolution rT3 are scaled linearly with lower module clock frequencies, as can be seen from the following formula: fT3 = Table 14-2 fTimer rT3 [ms] = 8 * 2 8 * 2 fTimer [MHz] Example for Timer 3 Frequencies and Resolutions fTimer [MHz] T3I FM1 fT3 [KHz] rT3 [ms] 24 7 0 23.44 42.67 24 0 1 6000.0 0.17 36 0 0 4500.0 0.22 36 4 0 281.25 3.55 36 7 1 70.31 14.22 This formula also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode. Data Sheet 191 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit x=3 Figure 14-3 Block Diagram of Core Timer T3 in Timer Mode Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘010B’ or ‘011B’. Bit T3M.0 (T3CON.3) selects the active level of the gate input. In gated timer mode the same options for the input frequency as for the timer mode are available. However, the input clock to the timer in this mode is gated by the external input line T3IN (Timer T3 External Input), which is an alternate function of P3.6. To enable this operation pin P3.6/T3IN must be configured as input, ie. direction control bit DP3.6 must contain ’0’. Data Sheet 192 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit x=3 Figure 14-4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M = ‘010B’, the timer is enabled when T3IN shows a low level. A high level at this line stops the timer. If T3M = ‘011B’, line T3IN must have a high level in order to enable the timer. In addition, the timer can be turned on or off by software using bit T3R. The timer will only run, if T3R = ‘1’ and the gate is active. It will stop, if either T3R = ‘0’ or the gate is inactive. Note: A transition of the gate signal at line T3IN does not cause an interrupt request. Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘001B’. In counter mode timer T3 is clocked by a transition at the external input pin T3IN, which is an alternate function of P3.6. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bit field T3I in control register T3CON selects the triggering transition (see Table 14-3 below). Data Sheet 193 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit x=3 Figure 14-5 Block Diagram of Core Timer T3 in Counter Mode Table 14-3 Core Timer T3 (Counter Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement 000 None. Counter T3 is disabled 001 Positive transition (rising edge) on T3IN 010 Negative transition (falling edge) on T3IN 011 Any transition (rising or falling edge) on T3IN 1XX Reserved. Do not use this combination For counter operation, a port pin P3.6/T3IN must be configured as input. The maximum input frequency which is allowed in counter mode is fTimer/8 (FM1 = ’1’). To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized, its level should be held high or low for at least 4 fTimer cycles (FM1 = ’1’) before it changes. Timer 3 in Incremental Interface Mode Incremental Interface mode for the core timer T3 is selected by setting bit field T3M in register T3CON to ‘110B’ or ‘111B’. In incremental interface mode pin P3.6/T3IN (configured as timer input T3IN) and pin P3.5/T3EUD (configured as timer input) are used to interface to an incremental encoder. Note: In the INCA-D, the T3EUD timer input is connected to P3.5. In this case, Timer 4 input T4IN can be used only by Software. Data Sheet 194 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit T3 is clocked by each transition on one or both of the external input lines which gives 2fold or 4-fold resolution of the encoder input. T3I T3R T3IN Edge detect T3 T3IR Up/Down T3OUT T3OTL T3EUD Phase detect T3OE XOR MUX T3UD T3UDE Figure 14-6 Block Diagram of Core Timer T3 in Incremental Interface Mode Bit field T3I in control register T3CON selects the triggering transitions (see table below). In this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. Depending on the chosen Incremental Intrerface Mode, Rotation detection ‘110B’ or Edge Detection ‘111B’, an interrupt can be generated. This interrupt is only generated if it’s enabled by setting bit T3IREN in register T3CON. For the Rotation detection an interrupt will be generated each time the count direction of timer 3 changes. For the Edge detection an interrupt will be generated each time a count action for timer 3 occurs. Count direction, changes in the count direction and count requests are monitored through the status bits T3RDIR, T3CHDIR and T3EDGE in register T3CON. T3 is modified automatically according to the speed and the direction of the incremental encoder. Therefore, the contents of timer T3 always represents the encoder’s current position. Table 14-4 Core Timer T3 (Incremental Interface Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement 000 None. Counter T3 stops. 001 Any transition (rising or falling edge) on T3IN. 010 Any transition (rising or falling edge) on T3EUD. Data Sheet 195 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Table 14-4 Core Timer T3 (Incremental Interface Mode) Input Edge Selection T3I Triggering Edge for Counter Increment / Decrement 011 Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD). 1XX Reserved. Do not use this combination The incremental encoder can be connected directly to the microcontroller without external interface logic. In a standard system, however, comparators will be employed to convert the encoder’s differential outputs (e.g. A, A) to digital signals (e.g. A). This greatly increases noise immunity. Note: The third encoder output T0, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer T3. External Encoder A A + - A B B + - B T0 T0 +- T0 T3input T3input Microcontroller Interrupt Signal Conditioning Figure 14-7 Interfacing the Encoder to the Microcontroller For incremental interface operation the following conditions must be met: l l l Bitfield T3M must be ’110B’ or ‘111B’. Pins associated to lines T3IN and T3EUD must be configured as input. Bit T3UDE must be ’1’ to enable automatic direction control. The maximum input frequency which is allowed in incremental interface mode is fTimer/8 (FM = 1). To ensure that a transition of any input signal is correctly recognized, its level should be held high or low for at least 4 fTimer cycles (FM = 1) before it changes. In Incremental Interface Mode the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. The table below summarizes the possible combinations. The figures below give examples of T3’s operation, visualizing count signal generation and direction control. It also shows how input jitter is compensated which might occur if the sensor rests near to one of its switching points. Data Sheet 196 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Table 14-5 Core Timer T3 (Incremental Interface Mode) Count Direction Level on respective other input T3IN Input Rising Falling Rising Falling High Down Up Up Down Low Up Down Down Up Forward Jitter Backward T3EUD Input Jitter Forward T3IN p U n ow U D Contents of T3 p T3EUD Note: This example shows the timer behavior assuming that T3 counts upon any transition on any input, i.e. T3I = ’011B’. Figure 14-8 Evaluation of the Incremental Encoder Signals Data Sheet 197 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Forward Jitter Backward Jitter Forward T3IN T3EUD n ow U p D U p Contents of T3 Note: This example shows the timer behavior assuming that T3 counts upon any transition on input T3IN, i.e. T3I = ’001B’. Figure 14-9 Evaluation of the Incremental Encoder Signals Note: Timer T3 operating in incremental interface mode automatically provides information on the sensor’s current position. Dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods. 14.1.2 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer, gated timer, counter, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The individual configuration for timers T2 and T4 is determined by their bitaddressable control registers T2CON and T4CON, which are both organized identically. Note that functions which are present in all 3 timers of timer block 1 are controlled in the same bit positions and in the same manner in each of the specific control registers. Run control for auxiliary timers T2 and T4 can be handled by the associated Run Control Bit T2R, T4R in register T2CON/T4CON. Alternatively, a remote control option (T2RC, T4RC = ’1’) may be enabled to start and stop T2/T4 via the run bit T3R of core timer T3. Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode, their operation is the same as described for the core timer T3. The descriptions, figures and tables apply accordingly with two exceptions: Data Sheet 198 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit l l There is no TxOUT output line for T2 and T4. Overflow/Underflow Monitoring is not supported (no output toggle latch). Timers T2 and T4 in Counter Mode In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input line TxIN, or by a transition of timer T3’s output toggle latch T3OTL. Figure 14-10 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input line, or at the output toggle latch T3OTL. Bit field TxI in the respective control register TxCON selects the triggering transition (see table below). Table 14-6 Auxiliary Timer (Counter Mode) Input Edge Selection T2I / T4I Triggering Edge for Counter Increment / Decrement X00 None. Counter Tx is disabled 001 Positive transition (rising edge) on TxIN 010 Negative transition (falling edge) on TxIN 011 Any transition (rising or falling edge) on TxIN 101 Positive transition (rising edge) of output toggle latch T3OTL 110 Negative transition (falling edge) of output toggle latch T3OTL 111 Any transition (rising or falling edge) of output toggle latch T3OTL Data Sheet 199 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. The maximum input frequency which is allowed in counter mode is fTimer/8 (FM1 = ’1’). To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized, its level should be held for at least 4 fTimer cycles (FM1 = ’1’) before it changes. Timer Concatenation Using the output toggle latch T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. Depending on which transition of T3OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit timer/counter. l l 32-bit Timer/Counter: If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T3. Thus, the two timers form a 32-bit timer. 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer+T3OTL+16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T3 can operate in timer, gated timer or counter mode in this case. Data Sheet 200 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit x = 2,4 y = 3 Note: Line ’*’ only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 14-11 Concatenation of Core Timer T3 and an Auxiliary Timer Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to ‘100B’. In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. The trigger signal is selected the same way as the clock source for counter mode (see table above), i.e. a transition of the auxiliary timer’s input or the output toggle latch T3OTL may trigger the reload. Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. Data Sheet 201 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Note: Line ’*’ only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 14-12 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register (T2 or T4) and the interrupt request flag (T2IR or T4IR) is set. Note: When a T3OTL transition is selected for the trigger signal, also the interrupt request flag T3IR will be set upon a trigger, indicating T3’s overflow or underflow. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. The reload mode triggered by T3OTL can be used in a number of different configurations. Depending on the selected active transition the following functions can be performed: l l l If both a positive and a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. This is the standard reload mode (reload on overflow/underflow). If either a positive or a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. Using this “single-transition” mode for both auxiliary timers allows to perform very flexible pulse width modulation (PWM). One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers. The figure below shows an example for the generation of a PWM signal using the alternate reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions). The PWM signal can be output on line T3OUT if the control bit T3OE is set Data Sheet 202 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit to ‘1’. With this method the high and low time of the PWM signal can be varied in a wide range. Note: The output toggle latch T3OTL is accessible via software and may be changed, if required, to modify the PWM signal. However, this will NOT trigger the reloading of T3. Note: An associated port pin linked to line T3OUT should be configured as output. Note: Lines ’*’ only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 14-13 GPT1 Timer Reload Configuration for PWM Generation Note: Although it is possible, it should be avoided to select the same reload trigger event for both auxiliary timers. In this case both reload registers would try to load the core timer at the same time. If this combination is selected, T2 is disregarded and the contents of T4 is reloaded. Data Sheet 203 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to ‘101B’. In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer's external input line TxIN. The capture trigger signal can be a positive, a negative, or both a positive and a negative transition. The two least significant bits of bit field TxI are used to select the active transition (see table in the counter mode section), while the most significant bit TxI.2 is irrelevant for capture mode. It is recommended to keep this bit cleared (TxI.2 = ‘0’). Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. Figure 14-14 Auxiliary Timer of Timer Block 1 in Capture Mode Upon a trigger (selected transition) at the corresponding input line TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set. Note: The direction control for T2IN and for T4IN must be set to 'Input', and the level of the capture trigger signal should be held high or low for at least 4 fTimer (FM1 = ’1’) cycles before it changes to ensure correct edge detection. Data Sheet 204 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit 14.2 Functional Description of Timer Block 2 Timer block 2 includes the two timers T5 (referred to as the auxiliary timer) and T6 (referred to as the core timer), and the 16-bit capture/reload register CAPREL. Each timer has an input line (TxIN) associated with it which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (Up / Down) may be programmed via software or may be dynamically altered by a signal at an external control input line. An overflow/underflow of core timer T6 is indicated by the output toggle latch T6OTL whose state may be output on related line T6OUT and on line T6OFL. The auxiliary timer T6 may be reloaded with the contents of CAPREL. The toggle bit also supports the concatenation of T6 with auxiliary timer T5, while concatenation of T6 with other timers is provided through line T6OFL. Triggered by an external signal, the contents of T5 can be captured into register CAPREL, and T5 may optionally be cleared. Both timer T6 and T5 can count up or down, and the current timer value can be read or modified by the CPU in the non-bitaddressable SFRs T5 and T6. T6OFL Figure 14-15 Structure of Timer Block 2 Data Sheet 205 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit 14.2.1 Core Timer T6 The operation of the core timer T6 is controlled by its bitaddressable control register T6CON. Timer 6 Run Bit The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit). Setting bit T6R to ‘1’ will start the timer, clearing T6R stops the timer. In gated timer mode, the timer will only run if T6R = ‘1’ and the gate is active (high or low, as programmed). Note: When bit T5RC = ’1’ bit T6R will also control (start and stop) auxiliary timer T5. Count Direction Control The count direction of the core timer can be controlled either by software or by the external input line T6EUD (Timer T6 External Up/Down Control Input). These options are selected by bits T6UD and T6UDE in control register T6CON. When the up/down control is done by software (bit T6UDE = ‘0’), the count direction can be altered by setting or clearing bit T6UD. When T6UDE = ‘1’, line T6EUD is selected to be the controlling source of the count direction. However, bit T6UD can still be used to reverse the actual count direction, as shown in the table below. If T6UD = ‘0’ and line T6EUD shows a low level, the timer is counting up. With a high level at T6EUD the timer is counting down. If T6UD = ‘1’, a high level at line T6EUD specifies counting up, and a low level specifies counting down. The count direction can be changed regardless of whether the timer is running or not. Table 14-7 Core Timer T6 Count Direction Control Line TxEUD Bit TxUDE Bit TxUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note: The direction control works the same for core timer T6 and for auxiliary timer T5. Therefore the lines and bits are named Tx... Data Sheet 206 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Timer 6 Overflow/Underflow Monitoring An overflow or underflow of timer T6 will clock the toggle latch T6OTL in control register T6CON. T6OTL can also be set or reset by software. Bit T6OE (Overflow/Underflow Output Enable) in register T6CON enables the state of T6OTL to be monitored via the external output line T6OUT. An associated port pin must be configured as output. In addition, T6OTL can be used in conjunction with the timer over/underflows as an input for the counter function of the auxiliary timer T5. For this purpose, the state of T6OTL does not have to be available at line T6OUT, because an internal connection is provided for this option. An overflow or underflow of timer T6 can also be used to clock other timers. For this purpose, there is the special output line T6OFL. Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to ‘000B’. In this mode, T6 is clocked with the module clock divided by a programmable prescaler, which is selected by bit field T6I. The input frequency fT6 for timer T6 and its resolution rT6 are scaled linearly with lower clock frequencies fTimer, as can be seen from the following formula: fT6 = fTimer rT6 [µs] = 4 * 2 4 * 2 fTimer [MHz] x=6 Figure 14-16 Block Diagram of Core Timer T6 in Timer Mode Data Sheet 207 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Timer 6 in Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to ‘010B’ or ‘011B’. Bit T6M.0 (T6CON.3) selects the active level of the gate input. In gated timer mode the same options for the input frequency as for the timer mode are available. However, the input clock to the timer in this mode is gated by the external input line T6IN (Timer T6 External Input). x=6 Figure 14-17 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M.0 = ‘0’ the timer is enabled when T6IN shows a low level. A high level at this line stops the timer. If T6M.0 = ‘1’ line T6IN must have a high level in order to enable the timer. In addition, the timer can be turned on or off by software using bit T6R. The timer will only run, if T6R = ‘1’ and the gate is active. It will stop, if either T6R = ‘0’ or the gate is inactive. Note: A transition of the gate signal at line T6IN does not cause an interrupt request. Timer 6 in Counter Mode Counter mode for the core timer T6 is selected by setting bit field T6M in register T6CON to ‘001B’. In counter mode timer T6 is clocked by a transition at the external input line T6IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at this line. Bit field T6I in control register T6CON selects the triggering transition (see table below). Data Sheet 208 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit x=6 Figure 14-18 Block Diagram of Core Timer T6 in Counter Mode Table 14-8 Core Timer T6 (Counter Mode) Input Edge Selection T6I Triggering Edge for Counter Increment / Decrement 000 None. Counter T6 is disabled 001 Positive transition (rising edge) on T6IN 010 Negative transition (falling edge) on T6IN 011 Any transition (rising or falling edge) on T6IN 1XX Reserved. Do not use this combination The maximum input frequency which is allowed in counter mode is fTimer/4 (FM2 = ’1’). To ensure that a transition of the count input signal which is applied to T6IN is correctly recognized, its level should be held high or low for at least 2 fTimer cycles (FM2 = ’1’) before it changes. 14.2.2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer, gated timer, or counter mode with the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The individual configuration for timer T5 is determined by its bitaddressable control register T5CON. Note that functions which are present in both timers of timer block 2 are Data Sheet 209 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit controlled in the same bit positions and in the same manner in each of the specific control registers. Run control for auxiliary timer T5 can be handled by the associated Run Control Bit T5R in register T5CON. Alternatively, a remote control option (T5RC = ’1’) may be enabled to start and stop T5 via the run bit T6R of core timer T6. Note: The auxiliary timer has no overflow/underflow toggle latch. Therefore, an output line for Overflow/Underflow Monitoring is not provided. Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6. The description and the table apply accordingly. Timer T5 in Timer Mode or Gated Timer Mode When the auxiliary timer T5 is programmed to timer mode or gated timer mode, its operation is the same as described for the core timer T6. The descriptions, figures and tables apply accordingly with two exceptions: l l There is no TxOUT line for T5. Overflow/Underflow Monitoring is not supported (no output toggle latch). Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register T5CON to ‘001B’. In counter mode timer T5, can be clocked by a transition of timer T6’s output toggle latch T6OTL only. x=5 Figure 14-19 Block Diagram of Auxiliary Timer T5 in Counter Mode Data Sheet 210 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at either the input line, or at the toggle latch T6OTL. Bit field T5P in control register T5CON selects the triggering transition (see table below). Table 14-9 Auxiliary Timer (Counter Mode) Input Edge Selection T5P Triggering Edge for Counter Increment / Decrement X00 None. Counter T5 is disabled 001 Positive transition (rising edge) on T5IN 010 Negative transition (falling edge) on T5IN 011 Any transition (rising or falling edge) on T5IN 101 Positive transition (rising edge) of output toggle latch T6OTL 110 Negative transition (falling edge) of output toggle latch T6OTL 111 Any transition (rising or falling edge) of output toggle latch T6OTL Note: Only state transitions of T6OTL which are caused by the overflows/underflows of T6 will trigger the counter function of T5. Modifications of T6OTL via software will NOT trigger the counter function of T5. The maximum input frequency which is allowed in counter mode is fTimer/4 (FM2 = ’1’). To ensure that a transition of the count input signal which is applied to T5IN is correctly recognized, its level should be held high or low for at least 2 fTimer cycles (FM2 = ’1’) before it changes. 14.2.3 Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer. Depending on which transition of T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33bit timer / counter. l l 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL is used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the two timers form a 32-bit timer. 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer+T6OTL+16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T6 can operate in timer, gated timer or counter mode in this case. Data Sheet 211 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit x =5 y = 6 Note: Line ’*’ only affected by over/underflows of T6, but NOT by software modifications of T6OTL. Figure 14-20 Concatenation of Core Timer T6 and Auxiliary Timer T5 Capture/Reload Register CAPREL in Capture Mode This 16-bit register can be used as a capture register for the auxiliary timer T5. This mode is selected by setting bit T5SC = ‘1’ in control register T5CON. Bit CT3 selects the external input line CAPIN or the input lines of timer T3 as the source for a capture trigger. Either a positive, a negative, or both a positive and a negative transition at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN or input T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bit field CI in register T5CON. The maximum input frequency for the capture trigger signal at CAPIN is fTimer/2 (FM2 = ’1’). To ensure that a transition of the capture trigger signal is correctly recognized, its level should be held for at least 2 fTimer cycles (FM2 = ’1’) before it changes. When the timer T3 capture trigger is enabled (CT3 = ’1’) register CAPREL captures the contents of T5 upon transitions of the selected input(s). These values can be used to measure T3’s input signals. This is useful e.g. when T3 operates in incremental interface mode, in order to derive dynamic information (speed acceleration) from the input signals. When a selected transition at the external input line CAPIN is detected, the contents of the auxiliary timer T5 are latched into register CAPREL, and interrupt request flag CRIR is set. With the same event, timer T5 can be cleared to 0000H. Data Sheet 212 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit This option is controlled by bit T5CLR in register T5CON. If T5CLR = ‘0’, the contents of timer T5 is not affected by a capture. If T5CLR = ‘1’, timer T5 is cleared after the current timer value has been latched into register CAPREL. Note: Bit T5SC only controls whether a capture is performed or not. If T5SC = ‘0’, the input line CAPIN can still be used to clear timer T5 or as an external interrupt input. This interrupt is controlled by the CAPREL interrupt control register CRIC. Figure 14-21 Timer Block 2 Register CAPREL in Capture Mode Timer Block 2 Capture/Reload Register CAPREL in Reload Mode This 16-bit register can be used as a reload register for the core timer T6. This mode is selected by setting bit T6SR = ‘1’ in register T6CON. The event causing a reload in this mode is an overflow or underflow of the core timer T6. When timer T6 overflows from FFFFH to 0000H (when counting up) or when it underflows from 0000H to FFFFH (when counting down), the value stored in register CAPREL is loaded into timer T6. This will not set the interrupt request flag CRIR associated with the CAPREL register. However, interrupt request flag T6IR will be set indicating the overflow/underflow of T6. Data Sheet 213 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Figure 14-22 Timer Block 2 Register CAPREL in Reload Mode Timer Block 2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits. This feature can be used to generate an output frequency that is a multiple of the input frequency. Data Sheet 214 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Figure 14-23 Timer Block 2 Register CAPREL in Capture-And-Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, that means, more 'ticks' within the time between two external events is required. For this purpose, the time between the external events is measured using timer T5 and the CAPREL register. Timer T5 runs in timer mode counting up with a frequency of e.g. fTimer/32. The external events are applied to line CAPIN. When an external event occurs, the timer T5 contents are latched into register CAPREL, and timer T5 is cleared (T5CLR = ‘1’). Thus, register CAPREL always contains the correct time between two events, measured in timer T5 increments. Timer T6, which runs in timer mode counting down with a frequency of e.g. fTimer/4, uses the value in register CAPREL to perform a reload on underflow. This means, the value in register CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since timer T6 runs 8 times faster than timer T5, it will underflow 8 times within the time between two external events. Thus, the underflow signal of timer T6 generates 8 'ticks'. Upon each underflow, Data Sheet 215 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit the interrupt request flag T6IR will be set and bit T6OTL will be toggled. The state of T6OTL may be output on line T6OUT. This signal has 8 times more transitions than the signal which is applied to line CAPIN. A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time units (e.g. T5 running at 1 MHz will capture the value 64H/100D for a 10 KHz input signal) while T6OTL will only toggle upon an underflow of T6 (i.e. the transition from 0000H to FFFFH). In the above mentioned example T6 would count down from 64H so the underflow would occur after 101 T6 timing ticks. The actual output frequency then is 79.2 KHz instead of the expected 80 KHz. This can be solved by activating the Capture Correction (CC = ’1’). If capture correction is active the content of T5 is decremented by 1 before being captured. The described deviation is eliminated (in the example T5 would capture 63H/99D and the output frequency is 80 KHz). The underflow signal of timer T6 can furthermore be used to clock one ore more of the timers of the CAPCOM units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events. This connection is accomplished via signal T6OFL. Data Sheet 216 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit 14.2.4 Programming the GPT Unit Several steps have to be done for getting a timer into operation. Figure 14-24 presents a block diagram of the software tasks controlling the GPT unit. • Port Initialization - Electrical Port Characteristic - Pin Function and Direction GPT Shell Initialization - Input Channel Selection (optional) GPT Kernel Initialization - Operation Mode Operating Frequency Resolution & Timer Operation - Enable Interrupt - Start Timer - Handle Interrupt Request Figure 14-24 Block Diagram of Software Tasks controlling a Timer Data Sheet 217 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit 14.3 GPT Registers All available registers are summarized in the overview table 14-10. Table 14-10 GPT12 Registers b/p1) Register Name Register Description Physical/8bit Address GPTCLC GPT Clock Control Register FE4C/26H T2CON Timer 2 Control Register FF40/A0H b 0000H T3CON Timer 3 Control Register FF42/A1H b 0000H T4CON Timer 4 Control Register FF44/A2H b 0000H T5CON Timer 5 Control Register FF46/A3H b 0000H T6CON Timer 6 Control Register FF48/A4H b 0000H CAPREL Capture/Reload Register FE4A/25H 0000H T2 Timer 2 Register FE40/20H 0000H T3 Timer 3 Register FE42/21H 0000H T4 Timer 4 Register FE44/22H 0000H T5 Timer 5 Register FE46/23H 0000H FE48/24H 0000H T6 1) Timer 6 Register b: bit addressable / p: bit protected Reset Value 0000H The clock control register is described in chapter 23.5. Function Control Registers The operating mode of the core timer T3 is configured and controlled via its bitaddressable control register T3CON. Timer 3 Control Register T3CON (FF42H / A1H) 15 14 13 12 T3 T3 T3 T3CH EDG IREN RDIR DIR E Data Sheet SFR-b 11 FM1 10 9 8 7 Reset Value: 0000H 6 T3 T3 T3OE T3UD T3R OTL UDE 218 5 4 T3M 3 2 1 0 T3I 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Field Bits Type Value Description T3I [2:0] rw Timer 3 Input Parameter Selection Timer mode see Table 14-11 for encoding Gated Timer see Table 14-11 for encoding Counter mode see Table 14-12 for encoding Incremental Interface mode see Table 14-13 for encoding T3M [5:3] rw 000 001 010 011 100 101 110 111 Timer 3 Mode Control Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high Reserved. Do not use this combination! Reserved. Do not use this combination! Incremental Interface Mode ( Rotation detection ) Incremental Interface Mode ( Edge detection ) 0 1 Timer 3 Run Bit Timer / Counter 3 stops Timer / Counter 3 runs 0 1 Timer 3 Up / Down Control (when T3UDE = ’0) Counting ’Up’ Counting ’Down’ T3R T3UD T3UDE 6 7 8 rw rw rw 0 1 T3OE 9 rw 0 1 T3OTL 10 rw 0/1 FM1 11 rw 0 1 Data Sheet Timer 3 External Up/Down Enable Counting direction is internally controlled by SW Counting direction is externally controlled by line T3EUD Overflow/Underflow Output Enable T3 overflow/underflow can not be externally monitored T3 overflow/underflow may be externally monitored via T3OUT Timer 3 Output Toggle Latch Toggles on each overflow / underflow of T3. Can be set or reset by software. Fast Mode for Timer Block 1 The maximum input frequency for Timer 2/3/4 is fTimer / 8. The maximum input frequency for Timer 2/3/4 is fTimer / 4. 219 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Field Bits Type Value Description T3EDGE 12 rw T3CHDIR 13 T3RDIR 14 T3IREN 15 0 1 Timer 3 Edge Detection The bit is set on each successful edge detection. The bit has to be reset by SW. No count edge was detected A count edge was detected 0 1 Timer 3 Count Direction Change The bit is set on a change of the countdirection of timer 3. The bit has to be reset by SW. No change in count direction was detected A change in count direction was detected 0 1 Timer 3 Rotation Direction Timer 3 counts up. Timer 3 counts down. rw r rw 0 1 Timer 3 Interrupt Enable Interrupt generation for T3CHDIR and T3EDGE is disabled. Interrupt generation for T3CHDIR and T3EDGE is enabled. Table 14-11 Timer 3 Input Parameter Selection for Timer mode and Gated mode T3I Prescaler for fTimer ( FM1 = 0 ) Prescaler for fTimer ( FM1 = 1 ) 000 8 4 001 16 8 010 32 16 011 64 32 100 128 64 101 256 128 110 512 256 111 1014 512 Table 14-12 Timer 3 Input Parameter Selection for Counter mode T3I Triggering Edge for Counter Update 000 None. Counter T3 is disabled 001 Positive transition ( raising edge ) on T3IN 010 Negative transition ( falling edge ) on T3IN 011 Any transition ( raising or falling edge ) on T3IN 1XX Reserved. Do not use this combination! Data Sheet 220 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Table 14-13 Timer 3 Input Parameter Selection for Incremental Interface mode T3I Triggering Edge for Counter Update 000 None. Counter T3 stops 001 Any transition ( raising or falling edge ) on T3IN 010 Any transition ( raising or falling edge ) on T3EUD 011 Any transition ( raising or falling edge ) on T3IN or T3EUD 1XX Reserved. Do not use this combination! Timer 2/4 Control Register T2CON (FF40H / A0H) SFR-b Reset Value: 0000H T4CON (FF44H / A2H) SFR-b Reset Value: 0000H 15 14 13 12 11 Tx Tx Tx TxCH EDG IREN RDIR DIR E 10 0 9 8 TxRC 7 6 Tx TxUD TxR UDE 5 4 TxM 3 2 1 0 TxI Field Bits Type Value Description TxI [2:0] rw Timer x Input Parameter Selection Timer mode see Table 14-14 for encoding Gated Timer see Table 14-14 for encoding Counter mode see Table 14-15 for encoding Incremental Interface mode see Table 14-16 for encoding TxM [5:3] rw TxR Data Sheet 6 000 001 010 011 100 101 110 111 Timer x Mode Control (Basic Operating Mode) Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high Reload Mode Capture Mode Incremental Interface Mode ( Rotation detection) Incermental Interface Mode ( Edge detection ) 0 1 Timer x Run Bit Timer / Counter x stops Timer / Counter x runs rw 221 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Field Bits Type Value Description TxUD 7 rw Timer x Up / Down Control (when TxUDE = ’0) Counting ’Up’ Counting ’Down’ 0 1 TxUDE 8 rw 0 1 TxRC 9 rw 0 1 Timer x External Up/Down Enable Counting direction is internally controlled by SW Counting direction is externally controlled by line TxEUD Timer x Remote Control Timer / Counter x is controlled by its own run bit TxR Timer / Counter x is controlled by the run bit of core timer 3 0 [11:10] r reserved for future use; reading returns 0; writing to these bit positions has no effect. TxEDGE 12 0 1 Timer x Edge Detection The bit is set on each successful edge detection. The bit has to be reset by SW. No count edge was detected A count edge was detected 0 1 Timer x Count Direction Change The bit is set on a change of the countdirection of timer x. The bit has to be reset by SW. No change in count direction was detected A change in count direction was detected 0 1 Timer x Rotation Direction Timer x counts up. Timer x counts down. TxCHDIR TxRDIR TxIREN 13 14 15 rw rw r rw 0 1 Data Sheet Timer x Interrupt Enable Interrupt generation for TxCHDIR and TxEDGE is disabled. Interrupt generation for TxCHDIR and TxEDGE is enabled. 222 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Table 14-14 Timer x Input Parameter Selection for Timer mode and Gated mode TxI Prescaler for fTimer ( FM1 = 0 ) Prescaler for fTimer ( FM1 = 1 ) 000 8 4 001 16 8 010 32 16 011 64 32 100 128 64 101 256 128 110 512 256 111 1014 512 Table 14-15 Timer x Input Parameter Selection for Counter mode TxI Triggering Edge for Counter Update X00 None. Counter Tx is disabled 001 reserved 010 reserved 011 reserved 101 Positive transition (rising edge) of output toggle latch T3OTL 110 Negative transition (falling edge) of output toggle latch T3OTL 111 Any transition (rising or falling edge) of output toggle latch T3OTL Table 14-16 Timer x Input Parameter Selection for Incremental Interface mode TxI Triggering Edge for Counter Update 00 None. Counter Tx stops 001 reserved 010 reserved 011 reserved 101 Positive transition (rising edge) of output toggle latch T3OTL 110 Negative transition (falling edge) of output toggle latch T3OTL 111 Any transition (rising or falling edge) of output toggle latch T3OTL Data Sheet 223 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Timer 6 Control Register T6CON (FF48H / A4H) 15 14 T6SR T6 CLR 13 12 0 SFR-b 11 FM2 10 9 8 7 Reset Value: 0000H 6 T6 T6 T6OE T6UD T6R OTL UDE 5 4 3 T6M 2 1 0 T6I Field Bits Type Value Description T6I [2:0] rw Timer 6 Input Parameter Selection Timer mode see Table 14-17 for encoding Gated Timer see Table 14-17 for encoding Counter mode see Table 14-18 for encoding T6M [5:3] rw 000 001 010 011 1xx Timer 6 Mode Control (Basic Operating Mode) Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high Reserved. Do not use this combination! 0 1 Timer 6 Run Bit Timer / Counter 6 stops Timer / Counter 6 runs 0 1 Timer 6 Up / Down Control (when T6UDE = ’0) Counting ’Up’ Counting ’Down’ T6R T6UD T6UDE 6 7 8 rw rw rw 0 1 T6OE 9 rw 0 1 T6OTL 10 rw 0/1 Data Sheet Timer 6 External Up/Down Enable Counting direction is internally controlled by SW Counting direction is externally controlled by line T6EUD Overflow/Underflow Output Enable T6 overflow/underflow can not be externally monitored T6 overflow/underflow may be externally monitored via T6OUT Timer 6 Output Toggle Latch Toggles on each overflow / underflow of T6. Can be set or reset by software. 224 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Field Bits Type Value Description FM2 11 rw Fast Mode for Timer Block 2 The maximum input frequency for Timer 5/6 is fTimer / 4. The maximum input frequency for Timer 5/6 is fTimer / 2. 0 1 0 [13:12] r reserved for future use; reading returns 0; writing to these bit positions has no effect. T6CLR 14 0 1 Timer 6 Clear Bit Timer 6 is not cleared on a capture event Timer 6 is cleared on a capture event 0 1 Timer 6 Reload Mode Enable Reload from register CAPREL Disabled Reload from register CAPREL Enabled T6SR 15 rw rw Table 14-17 Timer 6 Input Parameter Selection for Timer mode and Gated mode T6I Prescaler for fTimer ( FM2 = 0 ) Prescaler for fTimer ( FM2 = 1 ) 000 4 2 001 8 4 010 16 8 011 32 16 100 64 32 101 128 64 110 256 128 111 512 256 Table 14-18 Timer 6 Input Parameter Selection for Counter mode T6I Triggering Edge for Counter Update 000 None. Counter T6 is disabled 001 Positive transition ( raising edge ) on T6IN 010 Negative transition ( falling edge ) on T6IN 011 Any transition ( raising or falling edge ) on T6IN 1XX Reserved. Do not use this combination! Data Sheet 225 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Timer 5 Control Register T5CON (FF46H / A3H) 15 14 T5SC T5 CLR 13 12 CI SFR-b 11 CC 10 9 8 CT3 T5RC 7 Reset Value: 0000H 6 T5 T5UD T5R UDE 5 0 4 3 2 T5M 1 0 T5I Field Bits Type Value Description T5I [2:0] rw Timer 5 Input Parameter Selection Timer mode see Table 14-19 for encoding Gated Timer see Table 14-19 for encoding Counter mode see Table 14-20 for encoding T5M [4:3] rw Timer 5 Mode Control (Basic Operating Mode) Timer Mode Counter Mode Gated Timer with Gate active low Gated Timer with Gate active high 00 01 10 11 0 5 r reserved for future use; reading returns 0; writing to these bit positions has no effect. T5R 6 rw 0 1 Timer 5 Run Bit Timer / Counter 5 stops Timer / Counter 5 runs 0 1 Timer 5 Up / Down Control (when T5UDE = ’0) Counting ’Up’ Counting ’Down’ T5UD T5UDE 7 8 rw rw 0 1 T5RC 9 rw 0 1 CT3 CC Data Sheet 10 11 rw Timer 5 External Up/Down Enable Counting direction is internally controlled by SW Counting direction is externally controlled by line T5EUD Timer 5 Remote Control Timer / Counter 5 is controlled by its own run bit T5R Timer / Counter 5 is controlled by the run bit of core timer 6 (T6R) 0 1 Timer 3 Capture Trigger Enable Capture trigger from line CAPIN Capture trigger from T3 input lines 0 1 Capture Correction T5 is just captured T5 is decremented by 1 before being captured rw 226 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Field Bits Type Value CI [13:12] rw Register CAPREL Capture Trigger Selection (depending on bit CT3) Capture disabled Positive transition (rising edge) on CAPIN or any transition on T3IN Negative transition (falling edge) on CAPIN or any transition on T3EUD Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD 00 01 10 11 T5CLR 14 T5SC 15 Description rw 0 1 Timer 5 Clear Bit Timer 5 not cleared on a capture Timer 5 is cleared on a capture 0 1 Timer 5 Capture Mode Enable Capture into register CAPREL Disabled Capture into register CAPREL Enabled rw Table 14-19 Timer 5 Input Parameter Selection for Timer mode and Gated mode T5I Prescaler for fTimer ( FM2 = 0 ) Prescaler for fTimer ( FM2 = 1 ) 000 4 2 001 8 4 010 16 8 011 32 16 100 64 32 101 128 64 110 256 128 111 512 256 Table 14-20 Timer 5 Input Parameter Selection for Counter mode T5I Triggering Edge for Counter Update X00 None. Counter T5 is disabled 001 reserved 010 reserved Data Sheet 227 2003-03-31 INCA-D PSB 21473 General Purpose Timer Unit Table 14-20 Timer 5 Input Parameter Selection for Counter mode (cont’d) T5I Triggering Edge for Counter Update 011 reserved 101 Positive transition (rising edge) of output toggle latch T6OTL 110 Negative transition (falling edge) of output toggle latch T6OTL 111 Any transition (rising or falling edge) of output toggle latch T6OTL Timer and Reload registers T2 (FF40H ) SFR-b Reset Value: 0000H T3 (FF42H ) SFR-b Reset Value: 0000H T4 (FF44H ) SFR-b Reset Value: 0000H T5 (FF46H ) SFR-b Reset Value: 0000H T6 (FF48H ) SFR-b Reset Value: 0000H CAPREL (FF4AH) SFR-b Reset Value: 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Timer/Reload Value Data Sheet 228 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 15 The Asynchronous / Synchr. Serial Interface 15.1 Functional Description The ASC supports full-duplex asynchronous communication up to 1.5 MBaud and halfduplex synchronous communication up to 3 MBaud (@ 24 MHz CPU clock) . In synchronous mode, data are transmitted or received synchronous to a shift clock which is generated by CPU. In asynchronous mode, 8- or 9-bit data transfer, parity generation, and the number of stop bits can be selected. 15.1.1 Features Full duplex asynchronous operating modes • • • • • • • 8- or 9-bit data frames, LSB first Parity bit generation/checking One or two stop bits Baudrate from 1.5 MBaud to 0.3552 Baud (@24 MHz CPU clock) Multiprocessor mode for automatic address/data byte detection Loop-back capability Support for IrDA data transmission/reception up to max 115.2 KBaud Half-duplex 8-bit synchronous operating mode • Baudrate from 3 MBaud to 305.76 Baud (@ 24 MHz CPU clock) • Double buffered transmitter/receiver Interrupt generation • • • • on a transmitter buffer empty condition on a transmit last bit of a frame condition on a receiver buffer full condition on an error condition (frame, parity, overrun error) 15.1.2 Overview Figure 15-1 shows a block diagram of the ASC with its operating modes (asynchronous and synchronous mode.). Data Sheet 229 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface Prescaler / Fractional Divider fMOD fDIV Baudrate Timer Asynchronous Mode Serial Port Control RXD Mux IrDA Decoding fMOD ÷2 or ÷3 Receive / Transmit Buffers and Shift Registers Baudrate Timer IrDA Coding Mux TXD Synchronous Mode Serial Port Control TXD Shift Clock Receive / Transmit Buffers and Shift Registers RXDO RXDI Note: RXDI and RXDO are concatenated in the port logic to pin RXD. Figure 15-1 Block Diagram of the ASC Data Sheet 230 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 15.1.3 Register Description The ASC_P registers can be basically divided into three types of registers as shown in Figure 15-2. System Registers S0CLC S0CLC S0CON S0TBIC S0RIC Control Register Data Registers Interrupt Control S0CON S0TBUF S0RIC S0BG S0RBUF S0TBIC S0FDV IRQ14_STA S0PMW IRQ14_MSK Clock Control Register Control Register Transmit Buffer Interrupt Cotrol Receive Interrupt Control S0BG S0FDV S0PMW S0TBUF S0RBUF Baudrate Timer Reload Register Fractional Divider Register IrDA Pulse Mode and Width Register Transmit Buffer Register Receive Buffer Register (read only) Figure 15-2 SFRs associated with ASC_P1 Table 15-1 Name ASC_P Register Summary Address Reset Value Type 1) Description 16-Bit Register Mapping S0CLC FFBAH 0000H rw Clock Control Register 2) S0CON FFB0H 0000H rwh Control Register S0BG FEB4H 0000H rw Baudrate Timer Reload Register S0FDV FEB6H 0000H rw Fractional Divider Register S0PMW FEAAH 0000H rw IrDA Pulse Mode and Width Register S0TBUF FEB0H 0000H rw Transmit Buffer Register S0RBUF FEB2H 0000H r Receive Buffer Register S0TBIC F19CH 0000H rw Transmit Buffer Interrupt Control S0RIC FF6EH 0000H rw Receive Interrupt Control IRQ14_STA DF24H 0000H Combined Interrupt 14 Status Reg. IRQ14_MSK DF26H 0000H Combined Interrupt 14 Mask Reg. 1) 2) r: read only; w: write only; rw: read- and writeable; rwh: like rw, but SFR/bit is also affected by hardware. The ASC_P Clock Control Register CLC is physically located in the Bus Peripheral Interface. The table above defines only its register address not its content. The serial operating modes of the ASC module are controlled by its control register S0CON. This register contains control bits for mode and error check selection, and status flags for error identification. • Data Sheet 231 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface S0CON Control Register 15 R 14 LB 13 12 11 BRS ODD FDE 10 9 8 7 6 OE FE PE OEN FEN Field Bits Type Value Description M 2-0 rw STP REN 3 4 5 OEN 6 7 PEN/ REN RXDI 3 ST 2 1 0 M Mode Selection 8-bit data synchronous operation 8-bit data async. operation IrDA mode, 8-bit data async. operation 7-bit data + parity async. operation 9-bit data async. operation 8-bit data + wake up bit async. operation Reserved. Do not use this combination! 8-bit data + parity async. operation 0 1 Number of Stop Bit Selection One stop bit Two stop bits rw rwh rw Receiver Enable Control Receiver disabled Receiver enabled Bit is reset by hardware after reception of byte in synchronous mode. 0 1 Parity Check Enable / IrDA Input Inverter Enable All asynchronous modes without IrDA mode : Ignore parity errors Check parity errors Only in IrDA mode (M=010) : RXD input is not inverted RXD input is inverted 0 1 Framing Check Enable (async. operation only) Ignore framing errors Check framing errors 0 1 Overrun Check Enable Ignore overrun errors Check overrun errors 0 1 FEN 4 000 001 010 011 100 101 110 111 0 1 PEN / RXDI 5 rw rw PE 8 rwh Parity Error Flag Set by hardware on a parity error (PEN=’1’). Must be reset by software. FE 9 rwh Framing Error Flag Set by hardware on a framing error (FEN=’1’). Must be reset by software. Data Sheet 232 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface Field Bits Type Value Description OE 10 rwh FDE 11 rw Overrun Error Flag Set by hardware on an overrun error (OEN=’1’). Must be reset by software. 0 1 ODD 12 rw 0 1 BRS 13 rw 0 1 LB 14 rw 0 1 R – 15 31-16 rw 0 Fractional Divider Enable Fractional divider disabled Fractional divider is enabled and used as prescaler for baudrate timer (bit BRS is don’t care) Parity Selection Even parity selected (parity bit set on odd number of ‘1’s in data) Odd parity selected (parity bit set on even number of ‘1’s in data) Baudrate Selection Baudrate timer prescaler divide-by-2 selected Baudrate timer prescaler divide-by-3 selected BRS is don’t care if FDE=1 (fractional divider enabled) Loopback Mode Enable Loopback mode disabled Loopback mode enabled 0 1 Baudrate Generator Run Control Baudrate generator disabled (ASC_P inactive) Baudrate generator enabled BG should only be written if R=’0’. all reserved Note: Serial data transmission or reception is only possible when the run bit CON_R is set to ‘1’. Otherwise the serial interface is idle. Do not program the mode control field COM_M to one of the reserved combinations to avoid unpredictable behaviour of the serial interface. The baudrate timer reload register S0BG of the ASC module contains the 13-bit reload value for the baudrate timer in asynchronous and sychronous mode. Data Sheet 233 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface Baudrate Timer/Reload Register S0BG (FEB4H / 5AH) 15 14 13 0 0 0 12 SFR 11 10 9 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 BR_VALUE Field Bits Type Value Description BR_VALUE 12-0 rw all Baudrate Timer/Reload Register Value Reading BG returns the 13-bit content of the baudrate timer (bits 15....13 return 0); writing BG loads the baudrate timer reload register (bits 15....13 are don’t care). BG should only be written if CON_R=’0’. – 15-13 0 all reserved The fractional divider register S0FDV of the ASC module contains the 9-bit divider value for the fractional divider (asynchronous mode only). It is also used for reference clock generation of the autobaud detection unit. Fractional Divider Register S0FDV (FEB6H / 5BH) SFR 15 14 13 12 11 10 9 0 0 0 0 0 0 0 Reset Value: 0000H 8 7 6 5 4 3 2 1 0 FD_VALUE Field Bits Type Value Description FD_VALUE 8-0 rw all Fractional Divider Register Value FDV contains the 9-bit value n of the fractional divider which defines the fractional divider ratio: n/512 n=0-511). With n=0, the fractional divider is switched off (input=output frequency, fDIV = fMOD, see Figure 15-11). – 15-9 0 all reserved Data Sheet 234 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface The transmitter buffer register S0TBUF of the ASC module contains the transmit data value in asynchronous and synchronous modes. Transmitter Buffer Register S0TBUF (FEB0H / 58H) SFR 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 TD_VALUE Field Bits Type Value Description TD_VALUE 8-0 rw all Transmit Data Register Value TBUF contains the data to be transmitted in asynchronous and synchronous operating mode of the ASC. Data transmission is double buffered, Therefore, a new value can be written to TBUF before the transmission of the previous value is complete. – 15-9 0 all reserved The receiver buffer register S0RBUF of the ASC module contains the receive data value in asynchronous and synchronous modes. S0RBUF Transmitter Buffer Register S0RBUF (FEB2H / 59H) SFR 15 14 13 12 11 10 9 0 0 0 0 0 0 0 Data Sheet 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 RD_VALUE 235 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface Field Bits Type Value Description RD_VALUE 8-0 rw all Receive Data Register Value S0RBUF contains the reveived data bits and, depending on the selected mode, the parity bit in asynchronous and synchronous operating mode of the ASC. In asynchronous operating mode with M=011 (7bit data + parity) the received parity bit is written into RD7. In asynchronous operating mode with M=111 (8bit data + parity) the received parity bit is written into RD8. – 15-9 0 all reserved The IrDA pulse mode and width register S0PMW of the ASC module contains the 8-bit IrDA pulse width value and the IrDA pulse width mode select bit. This register is only required in the IrDA operating mode.. IrDA Pulse Mode/Width Register S0PMW (FEAAH / 55H) SFR 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 IRPW Reset Value: 0000H 7 6 Bits Type Value Description PW_VALUE 7-0 rw IRPW 8 rw – Data Sheet 15-9 0 4 3 2 1 0 PW_VALUE Field all 5 IrDA Pulse Width Value PW_VALUE is the 8-bit value n, which defines the variable pulse width of an IrDA pulse. Depending on the ASC_P input frequency fMOD, this value can be used to adjust the IrDA pulse width to value which is not equal 3/16 bit time (e.g. 1.6 µs). 0 1 IrDA Pulse Width Mode Control IrDA pulse width is 3/16 of the bit time IrDA pulse width is defined by PW_VALUE all reserved 236 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 15.1.4 General Operation Parity, framing, and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism to distinguish address from data bytes is included. Testing is supported by a loop-back option. A 13-bit baudrate timer with a versatile input clock divider circuitry provides the ASC with the serial clock signal. A transmission is started by writing to the Transmit Buffer register S0TBUF. Only the number of data bits which is determined by the selected operating mode will actually be transmitted, ie. bits written to positions 9 through 15 of register S0TBUF are always insignificant. Data transmission is double-buffered, so a new character may be written to the transmit buffer register, before the transmission of the previous character is complete. This allows the transmission of characters back-to-back without gaps. Data reception is enabled by the Receiver Enable Bit CON_REN. After reception of a character has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) Receive Buffer register S0RBUF. Bits in the upper half of S0RBUF which are not valid in the selected operating mode will be read as zeros. Data reception is double-buffered, so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register. In all modes, receive buffer overrun error detection can be selected through bit CON_OEN. When enabled, the overrun error status flag CON_OE and the error interrupt request line EIR will be acitvated when the receive buffer register has not been read by the time reception of a second character is complete. The previously received character in the receive buffer is overwritten. The Loop-Back option (selected by bit CON_LB) allows the data currently being transmitted to be received simultaneously in the receive buffer. This may be used to test serial communication routines at an early stage without having to provide an external network. In loop-back mode the alternate input/output function of port pins is not required. Note: Serial data transmission or reception is only possible when the Baudrate Generator Run Bit CON_R is set to ‘1’. Otherwise the serial interface is idle. Do not program the mode control field COM_M to one of the reserved combinations to avoid unpredictable behaviour of the serial interface 15.1.5 Asynchronous Operation Asynchronous mode supports full-duplex communication, where both transmitter and receiver use the same data frame format and the same baudrate. Data is transmitted on pin P3.10/TXD and received on pin P3.11/RXD. IrDA data transmission/reception is supported up to 115.2 KBit/s. Figure 15-3 shows the block diagram of the ASC_P3 when operating in asynchronous mode. Data Sheet 237 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface FDE 13-Bit Reload Register Fractional Divider fMOD fDIV MUX ÷2 fBR fBRT ÷3 R ÷16 13-Bit Baudrate Timer BRS M PE STP REN FEN PEN OEN LB Mux Sampling IrDA Decoding FE OE RIR Shift Clock TIR Serial Port Control Shift Clock TBIR EIR Receive Int. Request Transmit Int. Request Transmit Buffer Int. Request Error Int. Request Receive Shift Register Transmit Shift Register IrDA Coding Receive Buffer Reg. RBUF Transmit Buffer Reg. TBUF MUX Mux RXD Internal Bus TXD Figure 15-3 Asynchronous Mode of Serial Channel ASC_P3 15.1.5.1 Asynchronous Data Frames 8-Bit Data Frames 8-bit data frames either consist of 8 data bits D7...D0 (S0CON_M=’001B’), or of 7 data bits D6...D0 plus an automatically generated parity bit (S0CON_M=’011B’). Parity may be odd or even, depending on bit CON_ODD. An even parity bit will be set, if the moduloData Sheet 238 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 2-sum of the 7 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is enabled via bit CON_PEN (always OFF in 8-bit data mode). The parity error flag CON_PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit RBUF.7. 10-/11-Bit UART Frame 8 Data Bits S0CON_M=001 Start D0 Bit LSB 0 D1 D2 D3 D4 1 D5 D6 1 D7 (1st) (2nd) MSB Stop Stop Bit Bit 1 1 10-/11-Bit UART Frame 7 Data Bits S0CON_M=0 Start D0 Bit LSB 0 D1 D2 D3 D4 D5 D6 Parity (1st) (2nd) MSB Bit Stop Stop Bit Bit Figure 15-4 Asynchronous 8-Bit Frames 9-Bit Data Frames 9-bit data frames either consist of 9 data bits D8...D0 (S0CON_M=’100B’), of 8 data bits D7...D0 plus an automatically generated parity bit (S0CON_M=’111B’) or of 8 data bits D7...D0 plus wake-up bit (CON_M=’101B’). Parity may be odd or even, depending on bit CON_ODD. An even parity bit will be set, if the modulo-2-sum of the 8 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is enabled via bit CON_PEN (always OFF in 9-bit data and wake-up mode). The parity error flag CON_PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit RBUF.8. Data Sheet 239 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 11-/12-Bit UART Frame 9 Data Bits Start D0 Bit LSB 0 D1 D2 D3 D4 1 D5 D6 D7 1 (1st) (2nd) Bit 9 Stop Stop Bit Bit S0CON_M=100B : Bit 9 = Data Bit D8 S0CON_M=101B : Bit 9 = Wake-up Bit S0CON_M=111B : Bit 9 = Parity Bit Figure 15-5 Asynchronous 9-Bit Frames In wake-up mode received frames are only transferred to the receive buffer register, if the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be activated and no data will be transferred. This feature may be used to control communication in multi-processor system: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the additional 9th bit is a '1' for an address byte and a '0' for a data byte, so no slave will be interrupted by a data 'byte'. An address 'byte' will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8 LSBs of the received character (the address). The addressed slave will switch to 9-bit data mode (eg. by clearing bit CON_M.0), which enables it to also receive the data bytes that will be coming (having the wake-up bit cleared). The slaves that were not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. IrDA Frames The modulation schemes of IrDA is based on standard asynchronous data transmission frames. The asynchronous data format in IrDA mode (S0CON_M=010B) is defined as follows : 1 start bit / 8 data bits / 1 stop bit The coding/decoding of/to the asynchronous data frames is shown in Figure 15-6. In general, during the IrDA transmissions UART frames are encoded into IR frames and vice cersa. A low level on the IR frame indicates a “LED off“ state. A high level on the IR frame indicates a “LED on“ state. For a “0“ bit in the UART frame a high pulse is generated. For a “1“ bit in the UART frame no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixed Data Sheet 240 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface width of 3/16 of the bit time. The ASC_P also allows to program the length of the IrDA high pulse. Further, the polarity of the received IrDA pulse cane be inverted in IrAD mode. UART Frame Start Bit Stop Bit 8 Data Bits 0 1 0 1 0 0 1 1 0 1 IR Frame Start Bit 0 Bit Time Stop Bit 8 Data Bits 1 0 1 0 0 1 1/2 Bit Time 1 0 1 Pulse Width = 3/16 Bit Time (or variable length) Figure 15-6 IrDA Frame Encoding/Decoding 15.1.5.2 Asynchronous Transmission Asynchronous transmission begins at the next overflow of the divide-by-16 baudrate timer (transition of the baudrate clock fBR), if bit S0CON_R must be set and data has been loaded into S0TBUF. The transmitted data frame consists of three basic elements: • the start bit • the data field (8 or 9 bits, LSB first, including a parity bit, if selected) • the delimiter (1 or 2 stop bits) Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request line S0TBIR being activated. S0TBUF may now be loaded with the next data, while transmission of the previous one is still going on. The transmit interrupt request line S0TIR will be activated before the last bit of a frame is transmitted, ie. before the first or the second stop bit is shifted out of the transmit shift register. The transmitter output pin TXD must be configured for alternate data output’. Data Sheet 241 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 15.1.5.3 Asynchronous Reception Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD, provided that bits S0CON_R and S0CON_REN are set. The receive data input pin RXD is sampled at 16 times the rate of the selected baudrate. A majority decision of the 7th, 8th and 9th sample determines the effective bit value. This avoids erroneous results that may be caused by noise. If the detected value is not a '0' when the start bit is sampled, the receive circuit is reset and waits for the next 1-to-0 transition at pin RXD. If the start bit proves valid, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. When the last stop bit has been received, the content of the receive shift register is transferred to the receive data buffer register S0RBUF. Simultaneously, the receive interrupt request line RIR is activated after the 9th sample in the last stop bit time slot (as programmed), regardless whether valid stop bits have been received or not. The receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input pin. The receiver input pin RXD must be configured for input. Asynchronous reception is stopped by clearing bit S0CON_REN. A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Start bits that follow this frame will not be recognized. Note: In wake-up mode received frames are only transferred to the receive buffer register, if the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be activated and no data will be transferred. 15.1.5.4 IrDA Mode The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard also allows the pulse duration being independent of the baudrate or bit period. In this case the transmitted pulse has always the width corresponding to the 3/16 pulse width at 115.2 kBaud which is 1.627 µs. Both, bit period dependend or fixed IrDA pulse width generation can be selected. The IrDA pulse width mode is selected by bit PMW_IRPW. In case of fixed IrDA pulse width generation, the lower 8 bits in register PMW are used to adapt the IrDA pulse width to a fixed value of e.g. 1.627 µs. The fixed IrDA pulse width is generated by a programmable timer as shown in Figure 15-7. Data Sheet 242 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface PMW Start Timer tIPW fMOD IrDA Pulse 8-Bit Timer Figure 15-7 Fixed IrDA Pulse Generation The IrDA pulse width can be calculated according the formulas given in Table 15-2. Table 15-2 Formulas for the IrDA Pulse Width Calculation PMW PMW_IRPW 1 ... 255 0 1 Formulas t IPW = t IPW = 3 16 x Baudrate PMW fMOD t IPW min = (PMW >> 1) fMOD The name PMW in the formulas of Table 15-2 represents the content of the reload register PMW (PW_VALUE), taken as unsigned 8-bit integer. The content of PMW further defines the minimum IrDA pulse width (tIPW min) which is still recognized during a receive operation as a valid IrDA pulse. This function is independent of the selected IrDA pulse width mode (fixed or variable) which is defined by bit PMW_IRPW. The minimum IrDA pulse width is calculated by a shift right operation of PMW bit 7-0 by one bit divided by the module clock fMOD. Note: If PMW_IRPW=0 (fixed IrDA pulse width), PW_VALUE must be a value which assures that t IPW > t IPW min. Table 15-3 gives two examples for typical frequencies of fMOD. Table 15-3 IrDA Pulse Width Adaption to 1.627 µs fMOD PMW tIPW Error tIPW min 13 MHz 21 1.615 µs - 0.12 % 0.77 µs 25 MHz 41 1.64 µs + 0.8 % 0.8 µs Data Sheet 243 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 15.1.5.5 RXD/TXD Data Path Selection in Asynchronous Modes IrDA Coding IrDA Decode ASC_P1 Asynch. Mode Logic Mux Mux RXD Mux Figure 15-8 shows the asynchronous mode data paths. TXD S0CON LB RXDI M Figure 15-8 RXD/TXD Data Path in Asynchronous Modes (ASC_P1) 15.1.6 Synchronous Operation Synchronous mode supports half-duplex communication, basically for simple I/O expansion via shift registers. Data is transmitted and received via pin RXD while pin TXD outputs the shift clock. These signals are alternate functions of port pins. Synchronous mode is selected with S0CON_M=’000B’. 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baudrate generator. The shift clock is only active as long as data bits are transmitted or received. The lines RXDI and RXDO must be concatenated in the port logic to pin RXD. Data Sheet 244 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 13-Bit Reload Register fMOD ÷2 Mux fDIV fBR fBRT ÷3 R ÷4 13-Bit Baudrate Timer BRS M=000B OE RIR Shift Clock REN OEN LB TIR Serial Port Control Shift Clock TXD RXDI 0 MUX 1 TBIR EIR Receive Shift Register Transmit Shift Register Receive Buffer Reg. RBUF Transmit Buffer Reg. TBUF Receive Int. Request Transmit Int. Request Transmit Buffer Int. Request Error Int. Request RXDO Note: RXDI and RXDO are concatenated in the port logic to pin RXD. Internal Bus Figure 15-9 Synchronous Mode of Serial Channel ASC_P 15.1.6.1 Synchronous Transmission Synchronous transmission begins within 4 state times after data has been loaded into S0TBUF provided that S0CON_R is set and S0CON_REN=’0’ (half-duplex, no reception). Exception : in loopback mode (bit S0CON_LB set), S0CON_REN must be set for reception of the transmitted byte. Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request line TBIR being activated. S0TBUF may now be loaded with the next data, while transmission of the previous one is still going on. The Data Sheet 245 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface data bits are transmitted synchronous with the shift clock. After the bit time for the 8th data bit, both TXD and RXD will go high, the transmit interrupt request line TIR is activated, and serial data transmission stops. Pin P3.10/TXD must be configured for alternate data output in order to provide the shift clock. Pin P3.11/RXD must also be configured for output during transmission. 15.1.6.2 Synchronous Reception Synchronous reception is initiated by setting bit S0CON_REN=’1’. If bit S0CON_R=1, the data applied at RXD is clocked into the receive shift register synchronous to the clock which is output at pin TXD. After the 8th bit has been shifted in, the content of the receive shift register is transferred to the receive data buffer RBUF, the receive interrupt request line RIR is activated, the receiver enable bit S0CON_REN is reset, and serial data reception stops. Pin P3.10/TXD must be configured for alternate data output in order to provide the shift clock. Pin P3.11/RXD must be configured as alternate data input. Synchronous reception is stopped by clearing bit S0CON_REN. A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. If a previously received byte has not been read out of the receive buffer register at the time the reception of the next byte is complete, both the error interrupt request line EIR and the overrun error status flag S0CON_OE will be activated/set, provided the overrun check has been enabled by bit S0CON_OEN. 15.1.6.3 Synchronous Timing Figure 15-10 shows timing diagrams of the ASC synchronous mode data reception and data transmission. In idle state the shift clock is at high level. With the beginning of a synchronous transmission of a data byte the data is shifted out at RXD with the falling edge of the shift clock. If a data byte is received through RXD data is latched with the rising edge of the shift clock. Between two consecutive receive or transmit data bytes one shift clock cycle (fBR) delay is inserted. Data Sheet 246 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface Shift Receive/Transmit Timing Shift Shift Latch Latch Shift Clock Transmit Data Data Bit n Data Bit n+1 Data Bit n+2 Receive Data Valid Data n Valid Data n+1 Valid Data n+2 Continuous Transmit Timing Shift Clock Transmit Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 1. Byte Receive Data D0 D1 D2 D3 D4 D2 D3 2. Byte D5 D6 1. Byte D7 D0 D1 D2 D3 2. Byte Figure 15-10 ASC_P3 Synchronous Mode Waveforms 15.1.7 Baudrate Generation The serial channel ASC has its own dedicated 13-bit baudrate generator with 13-bit reload capability, allowing baudrate generation independent of the GPT timers. The baudrate generator is clocked with a clock (fDIV) which is derived via a prescaler from the ASC input clock fMOD, e.g. 36 MHz. The baudrate timer is counting downwards and can be started or stopped through the baudrate generator run bit S0CON_R. Each underflow of the timer provides one clock pulse to the serial channel. The timer is reloaded with the value stored in its 13-bit reload register each time it underflows. The resulting clock fBRT is again divided by a factor for the baudrate clock (± 16 in asynchronous modes and ± 4 in synchronous mode). The prescaler is selected by the bits S0CON_BRS and S0CON_FDE. In the asynchronous operating modes, additionally to the two fixed dividers a fractional divider prescaler unit is available which allows to select prescaler divider ratios of n/512 with n=0-511. Therefore, the baudrate of ASC is Data Sheet 247 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface determined by the module clock, the content of S0FDV, the reload value of S0BG and the operating mode (asynchronous or synchronous). Register S0BG is the dual-function Baudrate Generator/Reload register. Reading BG returns the content of the timer BR_VALUE (bits 15...13 return zero), while writing to S0BG always updates the reload register (bits 15...13 are insiginificant). An auto-reload of the timer with the content of the reload register is performed each time S0CON_BG is written to. However, if S0CON_R=’0’ at the time the write operation to BG is performed, the timer will not be reloaded until the first instruction cycle after S0CON_R=’1’. For a clean baudrate initialization S0BG should only be written if S0CON_R=’0’. If S0BG is written with S0CON_R=’1’, an unpredicted behaviour of the ASC may occur during running transmit or receive operations. 15.1.7.1 Baudrates in Asynchronous Mode For asynchronous operation, the baudrate generator provides a clock fBRT with 16 times the rate of the established baudrate. Every received bit is sampled at the 7th, 8th and 9th cycle of this clock. The clock divider circuitry, which generates the input clock for the 13bit baudrate timer, is extended by a fractional divider circuitry, which allows the adjustment of more accurate baudrates and the extension of the baudrate range. The baudrate of the baudrate generator depends on the following input clock, bits and register values : • • • • Input clock fMOD Selection of the baudrate timer input clock fDIV by bits S0CON_FDE and S0CON_BRS If bit S0CON_FDE=1 (fractional divider) : value of register S0CON_FDV value of the 13-bit reload register S0BG The output clock of the baudrate timer with the reload register is the sample clock in the asynchronous modes of the ASC. For baudrate calculations, this baudrate clock fBR is derived from the sample clock fDIV by a division by 16. Data Sheet 248 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 13-Bit Reload Register FDE Fractional Divider fMOD ÷16 Mux ÷2 R fDIV 13-Bit Baudrate Timer fBR Baud Rate Clock Sample Clock fBRT ÷3 BRS FDE BRS Selected Divider 0 0 ÷2 0 1 ÷3 1 X Fractional Divider Figure 15-11 ASC Baudrate Generator Circuitry in Asynchronous Modes Using the fixed Input Clock Divider The baudrate for asynchronous operation of serial channel ASC when using the fixed input clock divider ratios (S0CON_FDE=0) and the required reload value for a given baudrate can be determined by the following formulas : Table 15-4 Asynchronous Baudrate Formulas using the Fixed Input Clock Dividers FDE BRS BG 0 0 0 ... 8191 Formula Baudrate = BG = 1 Baudrate = BG = Data Sheet 249 fMOD 32 x (BG+1) fMOD 32 x Baudrate -1 fMOD 48 x (BG+1) fMOD -1 48 x Baudrate 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface BG represents the contents of the reload register S0BG (BR_VALUE), taken as unsigned 13-bit integer. The maximum baudrate that can be achieved for the asynchronous modes when using the two fixed clock dividers and a module clock of 24 MHz is 0.5 MBaud. Table 15-5 below lists various commonly used baudrates together with the required reload values and the deviation errors compared to the intended baudrate. Table 15-5 Typical Asynchronous Baudrates using the Fixed Input Clock Dividers Baudrate BRS = ‘0’, fMOD = 24 MHz BRS = ‘1’, fMOD = 24 MHz Deviation Error Reload Value Deviation Error Reload Value 19.2 KBaud + 0.16 % 0026H + 0.16 % 0019H 9600 Baud + 0.16 % 004CH + 0.16 % 0033H Note: S0CON_FDE must be 0 to achieve the baudrates in the table above. The deviation errors given in the table above are rounded. Using a baudrate crystal will provide correct baudrates without deviation errors. Using the Fractional Divider When the fractional divider is selected, the input clock fDIV for the baudrate timer is derived from the module clock fMOD by a programmable divider. If S0CON_FDE=1, the fractional divider is activated, It divides fMOD by a fraction of n/512 for any value of n from 0 to 511. If n=0, the divider ratio is 1 which means that fDIV=fMOD. In general, the fractional divider allows to program the baudrrate with a much better accuracy than with the two fixed prescaler divider stages. Table 15-6 Asynchronous Baudrate Formulas using the Fractional Input Clock Divider FDE BRS BG FDV Formula 1 X 1 ... 8191 1 ... 511 0 Baudrate = Baudrate = FDV 512 x fMOD 16 x (BG+1) fMOD 16 x (BG+1) BG represents the content of the reload register S0BG (BR_VALUE), taken as unsigned 13-bit integer. FDV represents the content of the fractional divider register S0FDV (FD_VALUE) taken as unsigned 9-bit integer. For example, typical asynchronous baudrates are shown in Table 15-7. Data Sheet 250 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface Using the fractional divider and a module clock of 24 MHz (equal to the INCA-D CPU clock) the available baudrate range is 1 MBaud down to 0.5364 Baud. . Table 15-7 fMOD Typical Asynchronous Baudrates using the Fractional Input Clock Divider Desired Baudrate BG FDV Resulting Baudrate Deviation < 0.03 % 57.6 kBaud 20 413 57617 38.4 kBaud 27 367 38.400 kBaud 0% 19.2 kBaud 55 367 19.200 kBaud 0% 8191 1 0.53644 Baud min. Baudrate 0% Note: The ApNote AP2423 provides a program ’ASC.EXE’ which allows to calculate values for the S0FDV and S0BG registers depending on fMOD, the requested baudrate, and the maximum deviation. Please contact your Infineon Technologies representative. 15.1.7.2 Baudrates in Synchronous Mode For synchronous operation, the baudrate generator provides a clock with 4 times the rate of the established baudrate.(see Figure 15-12). Data Sheet 251 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 13-Bit Reload Register ÷2 fMOD fDIV Mux 13-Bit Baudrate Timer ÷3 fBRT Shift / Sample Clock ÷4 R BRS BRS Selected Divider 0 ÷2 1 ÷3 Figure 15-12 ASC Baudrate Generator Circuitry in Synchronous Mode The baudrate for synchronous operation of serial channel ASC can be determined by the formulas as shown in Table 15-8. Table 15-8 Synchronous Baudrate Formulas BRS BG 0 0 ... 8191 Formula Baudrate = 1 Baudrate = fMOD 8 x (BG+1) BG = fMOD 8 x Baudrate -1 fMOD 12 x (BG+1) BG = fMOD 12 x Baudrate -1 BG represents the content of the reload register S0BR (BR_VALUE), taken as unsigned 13-bit integers. The maximum baudrate that can be achieved in synchronous mode when using a module clock of 36 MHz is 4.5 MBaud. Data Sheet 252 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface 15.1.8 Hardware Error Detection Capabilities To improve the safety of serial data exchange, the serial channel ASC provides an error interrupt request flag, which indicates the presence of an error, and three (selectable) error status flags in register S0CON, which indicate which error has been detected during reception. Upon completion of a reception, the error interrupt request line S0EIR will be activated simultaneously with the receive interrupt request line S0RIR, if one or more of the following conditions are met : – the framing error detection enable bit S0CON_FEN is set and any of the expected stop bits is not high, the framing error flag S0CON_FE is set, indicating that the error interrupt request is due to a framing error (Asynchronous mode only). – If the parity error detection enable bit S0CON_PEN is set in the modes where a parity bit is received, and the parity check on the received data bits proves false, the parity error flag S0CON_PE is set, indicating that the error interrupt request is due to a parity error (Asynchronous mode only). – If the overrun error detection enable bit S0CON_OEN is set and the last character received was not read out of the receive buffer by software or DMA transfer at the time the reception of a new frame is complete, the overrun error flag S0CON_OE is set indicating that the error interrupt request is due to an overrun error (Asynchronous and synchronous mode). 15.1.9 Interrupts There are four different interrupts associated with the serial channel ASC. S0TIR indicates a transmit interrupt, S0TBIR indicates a transmit buffer interrupt, S0IR indicates a receive interrupt and S0EIR indicates an error interrupt of the serial channel. The cause of an error interrupt request (framing, parity, overrun error) can be identified by the error status flags FE, PE, and OE which are located in the control register S0CON. For normal operation (ie. besides the error interrupt) the ASC provides three interrupt requests to control data exchange via the serial channel: • S0TBIR is activated when data is moved from S0TBUF to the transmit register • S0TIR is activated before the last bit of an async. frame is transmitted, or after the last bit of a synchronous frame has been transmitted • S0RIR is activated when the received frame is moved to S0RBUF. S0TBIR and S0RIR are connected to dedicated interrupt nodes of the CPU, whereas SEIR and STIR are part of the combined interrupt node COMB2INT (refer to "Interrupt System Structure" on page 8-85). The transmitter is serviced by two interrupt handlers. This provides advantages for the servicing software. For single transfers it is sufficient to use the transmitter interrupt (S0TIR), which indicates that the previously loadad data has been transmitted, except for the last bit of an asynchronous frame.) Data Sheet 253 2003-03-31 INCA-D PSB 21473 The Asynchronous / Synchr. Serial Interface For multiple back-to-back transfers it is necessary to load the next piece of data at last until the time the last bit of the previous frame has been transmitted. In asynchronous mode this leaves just one bit-time for the handler to respond to the transmitter interrupt request, in synchronous mode it is impossible at all. Using the transmit buffer interrupt (S0TBIR) to reload transmit data gives the time to transmit a complete frame for the service routine, as TBUF may be reload while the previous data is still being transmitted. Data Sheet 254 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces 16 The High-Speed Synchronous Serial Interfaces The INCA-D comprises two High-Speed Synchronous Serial Interfaces SSC0 and SSC1. These interfaces provide flexible high-speed serial communication between the INCA-D and other microcontrollers, microprocessors or external peripherals. The SSCs support full-duplex and half-duplex synchronous communication up to 12.5 MBaud. The serial clock signals can be generated by the SSCs itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baud rate generator provides each of the the SSC with a separate serial clock signal. The high-speed synchronous serial interfaces can be configured in a very flexible way, so they can be used with other synchronous serial interfaces (eg. the ASC in synchronous mode), serve for master/slave or multimaster interconnections or operate compatible with the popular SPI interface. So they can be used to communicate with shift registers (IO expansion), peripherals (eg. EEPROMs etc.) or other controllers (networking). The SSCs support half-duplex and full-duplex communication. Data is transmitted or received for SSC0 on pins MTSR0/P3.9 (Master Transmit / Slave Receive) and MRST0/P3.8 (Master Receive / Slave Transmit) and for SSC1 on the pins MTSR1/P3.1 and MRST1/P3.0 respectively. The clock signals are output or input on pin SCLK0/P3.13 or SCLK1/P3.2 respectively. These pins are alternate functions of Port 3 pins. Figure 16-1 and Figure 16-2 give an overview about the used registers to control the two SSCs. Data Sheet 255 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Ports & Direction Control Alternate Functions Data Registers ODP3E SSC0BRE DP3 SSC0TBE P3 SSC0RBE Control Registers SSC0CON SSC0CLC SSC0TIC SSC0RIC IRQ14_STA IRQ14_MSK SCLK0 / P3.13 MTSR0/ P3.9 MRST0 / P3.8 ODP3 DP3 SSC0BR SSC0TB SSC0TIC Interrupt Control Port 3 Open Drain Control Register Port 3 Direction Control Register SSC0 Baud Rate Generator/Reload Register SSC0 Transmit Buffer Register SSC0 Transmit Interrupt Control Register P3 Port 3 Data Register SSC0CONSSC0 Control Register SSC0CLC SSC0 Clock Control Register SSC0RB SSC0 Receive Buffer Register SSC0RIC SSC0 Receive Interrupt Control Register IRQ14_STA Combined Interrupt Control Register Figure 16-1 SFRs and Port Pins associated with the SSC0 Ports & Direction Control Alternate Functions Data Registers ODP3E SSC1BRE DP3 SSC1TBE P3 SSC1RBE Control Registers SSC1CON SSC1TIC SSC1RIC SSC1CLC IRQ14_STA IRQ14_MSK SCLK1 / P3.2 MTSR1 / P3.1 MRST1 / P3.0 ODP3 DP3 SSC1BR SSC1TB SSC1TIC Interrupt Control Port 3 Open Drain Control Register Port 3 Direction Control Register SSC1 Baud Rate Generator/Reload Register SSC1 Transmit Buffer Register SSC1 Transmit Interrupt Control Register P3 Port 3 Data Register SSC1CONSSC1 Control Register SSC1CLC SSC1 Clock Control Register SSC1RB SSC1 Receive Buffer Register SSC1RIC SSC1 Receive Interrupt Control Register Figure 16-2 SFRs and Port Pins associated with the SSC1 Data Sheet 256 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Figure 16-3 Synchronous Serial Channel SSC Block Diagram (SSC0 and SSC1) The clock control register SSC0CLC is located at F0B6H and SS1CLC can be found at F058H (see Chapter 23.5) The operating mode of the serial channels SSC0 and SSC1 is controlled by their bitaddressable control register SSC0CON or SSC1CON respectively. The registers serve for two purposes: Note: The following descriptions are valid for SSC0 as well as for SSC1. • during programming (SSC0 disabled by SSCEN0=’0’) they provide access to a set of control bits, • during operation (SSC0 enabled by SSC0EN=’1’) it provides access to a set of status Data Sheet 257 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces flags. Register SSC0CON is shown below in each of the two modes. Because the register descriptions are valid for SSC0 and SSC1, the corresponding bits are generally denoted by ’x’. This means ’x’ is the placeholder for ’1’ and ’2’ respectively SSC0CON (FFB2H / D9H) 15 14 SSCx SSCx EN=0 MS rw rw 13 - 12 SSC1CON (FF5EH / AFH) 11 10 9 8 7 SSCx SSCx SSCx SSCx SSCx AREN BEN PEN REN TEN rw rw rw rw rw - SFRs 6 5 Reset Value: 0000H 4 3 SSCx SSCx SSCx PO PH HB rw rw rw 2 1 0 SSCxBM rw Bit Function (Programming Mode, SSCxEN = ‘0’) SSCxBM SSCx Data Width Selection 0: Reserved. Do not use this combination. 1...15 : Transfer Data Width is 2...16 bit (+1) SSCxHB SSCx Heading Control Bit 0: Transmit/Receive LSB First 1: Transmit/Receive MSB First SSCxPH SSCx Clock Phase Control Bit 0: Shift transmit data on the leading clock edge, latch on trailing edge 1: Latch receive data on leading clock edge, shift on trailing edge SSCxPO SSCx Clock Polarity Control Bit 0: Idle clock line is low, leading clock edge is low-to-high transition 1: Idle clock line is high, leading clock edge is high-to-low transition SSCxTEN SSCx Transmit Error Enable Bit 0: Ignore transmit errors 1: Check transmit errors SSCxREN SSCx Receive Error Enable Bit 0: Ignore receive errors 1: Check receive errors SSCxPEN SSCx Phase Error Enable Bit 0: Ignore phase errors 1: Check phase errors SSCxBEN SSCx Baudrate Error Enable Bit 0: Ignore baudrate errors 1: Check baudrate errors SSCxAREN SSCx Automatic Reset Enable Bit 0: No additional action upon a baudrate error 1: The SSCx is automatically reset upon a baudrate error Data Sheet 258 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Bit Function (Programming Mode, SSCxEN = ‘0’) SSCxMS SSCx Master Select Bit 0: Slave Mode. Operate on shift clock received via SCLK. 1: Master Mode. Generate shift clock and output it via SCLK. SSCxEN SSCx Enable Bit = ‘0’ Transmission and reception disabled. Access to control bits. SSC0CON (FFB2H / D9H) 15 14 SSCx SSCx EN=1 MS rw rw 13 - 12 SSC1CON (FF5EH / AFH) 11 10 9 8 SSCx SSCx SSCx SSCx SSCx BSY BE PE RE TE r rw rw rw rw SFRs Reset Value: 0000H 7 6 5 4 3 2 1 - - - - SSCxBC - - - - r 0 Bit Function (Operating Mode, SSCxEN = ‘1’) SSCxBC SSCx Bit Count Field Shift counter is updated with every shifted bit. Do not write to!!! SSCxTE SSCx Transmit Error Flag 1: Transfer starts with the slave’s transmit buffer not being updated SSCxRE SSCx Receive Error Flag 1: Reception completed before the receive buffer was read SSCxPE SSCx Phase Error Flag 1: Received data changes around sampling clock edge SSCxBE SSCx Baudrate Error Flag 1: More than factor 2 or 0.5 between Slave’s actual and expected baudrate SSCxBSY SSCx Busy Flag Set while a transfer is in progress. Do not write to!!! SSCxMS SSCx Master Select Bit 0: Slave Mode. Operate on shift clock received via SCLK. 1: Master Mode. Generate shift clock and output it via SCLK. SSCxEN SSCx Enable Bit = ‘1’ Transmission and reception enabled. Access to status flags and M/S control. Note: The target of an access to SSCxCON (control bits or flags) is determined by the state of SSCxEN prior to the access, ie. writing C057H to SSCxCON in programming mode (SSCxEN=’0’) will initialize the SSCx (SSCxEN was ‘0’) and then turn it on (SSCxEN=’1’). When writing to SSCxCON, make sure that reserved locations receive zeros. Data Sheet 259 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces The SSCx baud rate timer reload register SSCxBR containthe 16-bit reload value for the baud rate timer. SSC0BR (F0B4H / 5AH) 15 14 13 12 SSC1BR (F05EH / 2FH) 11 10 9 8 7 ESFRs 6 5 4 Reset Value: 0000H 3 2 1 0 SSCx SSCx SSCx SSCx SSCx SSxC SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx RL15 RL14 RL13 RL12 RL11 RL10 RL9 RL8 RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function SSCxRL15-0 Baud Rate Timer/Reload Register Value Reading SSCxxBG returns the 16-bit content of the baud rate timer. Writing SSCxxBG loads the baud rate timer reload register. rw The SSCx transmitter buffer register SSCxTB contain the transmit data value. SSC0TB (F0B0H / 58H) 15 14 13 12 SSC1TB (F05AH / 2DH) 11 10 9 8 7 ESFR 6 Reset Value: 0000H 5 4 3 2 1 0 SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx TD15 TD14 TD13 TD12 TD11 TD10 TD9 TD8 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 rw rw rw Bit rw rw rw rw rw rw rw rw rw rw rw rw rw Function SSCxxTD15-0 Transmit Data Register Value SSCxTB contains the data to be transmitted. Unselected bits of SSCxTB are ignored during transmission. The SSCx receiver buffer register SSCxRB contains the receive data value. SSC0RB (F0B2H / 59H) 15 14 13 12 SSC1RB (F05CH / 2EH) 11 10 9 8 7 ESFRs 6 5 Reset Value: 0000H 4 3 2 1 0 SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx SSCx RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 r r r r r r r r r r r r r r r r Bit Function SSCxRD7-0 Receive Data Register Value SSCxRB contains the reveived data bits. Unselected bits of SSC0RB will be not valid and should be ignored The shift registers of SSC0 and SSC1 are connected to both the transmit pin and the receive pin via the pin control logic (see block diagram). Transmission and reception of serial data is synchronized and takes place at the same time, ie. the same number of Data Sheet 260 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces transmitted bits is also received. Transmit data is written into the Transmit Buffer SSCxTB. It is moved to the shift register as soon as this is empty. An SSC-master (SSCxMS=’1’) immediately begins transmitting, while an SSC-slave (SSCxMS=’0’) will wait for an active shift clock. When the transfer starts, the busy flag SSCxBSY is set and a transmit interrupt request (SSCxTIR) will be generated to indicate that SSCxTB may be reloaded again. When the programmed number of bits (2...16) has been transferred, the contents of the shift register are moved to the Receive Buffer SSCxRB and a receive interrupt request (SSCxRIR) will be generated. If no further transfer is to take place (SSCxTB is empty), SSCxBSY will be cleared at the same time. Software should not modify SSCxBSY, as this flag is hardware controlled. The transfer of serial data bits can be programmed in many respects: • the data width can be chosen from 2 bits to 16 bits • transfer may start with the LSB or the MSB • the shift clock may be idle low or idle high • data bits may be shifted with the leading or trailing edge of the clock signal • the baudrate may be set from 274.7 Baud up to 9 MBd (@ 36 MHz CPU clock) • the shift clock can be generated (master) or received (slave) This allows the adaptation of the SSCs to a wide range of applications, where serial data transfer is required. The Data Width Selection supports the transfer of frames of any length, from 2-bit “characters” up to 16-bit “characters”. Starting with the LSB (SSCxHB=’0’) allows communication eg. with ASC devices in synchronous mode (C166 family) or 8051 like serial interfaces. Starting with the MSB (SSCHB=’1’) allows operation compatible with the SPI interface. Regardless which data width is selected and whether the MSB or the LSB is transmitted first, the transfer data is always right aligned in registers SSCxTB and SSCxRB, with the LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the internal shift register logic. The unselected bits of SSCxTB are ignored, the unselected bits of SSCxRB will be not valid and should be ignored by the receiver service routine. The Clock Control allows the adaptation of transmit and receive behaviour of the SSCx to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out transmit data, while the other clock edge is used to latch in receive data. Bit SSCxPH selects the leading edge or the trailing edge for each function. Bit SSCxPO selects the level of the clock line in the idle state. So for an idle-high clock the leading edge is a falling one, a 1-to-0 transition. The figure below is a summary. Data Sheet 261 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Figure 16-4 Serial Clock Phase and Polarity Options 16.1 Full-Duplex Operation The different devices are connected through three lines. The definition of these lines is always determined by the master: The line connected to the master's data output pin MTSRx is the transmit line, the receive line is connected to its data input line MRSTx, and the clock line is connected to pin SCLKx. Only the device selected for master operation generates and outputs the serial clock on pin SCLKx. All slaves receive this clock, so their pin SCLKx must be switched to input mode. The output of the master’s shift register is connected to the external transmit line, which in turn is connected to the slaves’ shift register input. The output of the slaves’ shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave. The external connections are hard-wired, the function and direction of these pins is determined by the master or slave operation of the individual device. Note: The shift direction shown in the figure applies for MSB-first operation as well as for LSB-first operation. When initializing the devices in this configuration, select one device for master operation (SSCxMS=’1’), all others must be programmed for slave operation (SSCxMS=’0’). Initialization includes the operating mode of the device's SSCx and also the function of the respective port lines (see “Port Control”). Data Sheet 262 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Master Device #1 Device #2 Shift Register MTSR MRST Clock Slave Shift Register SCLK Transmit Receive MTSR MRST Clock SCLK Clock Slave Device #3 Shift Register MTSR MRST SCLK Clock MCS01963 Figure 16-5 Full Duplex Configuration (valid for SSC0 and SSC1) The data output pins MRSTx of all slave devices are connected together onto the one receive line in this configuration. During a transfer each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: Only one slave drives the line, ie. enables the driver of its MRSTx pin. All the other slaves have to program their MRSTx pins to input. So only one slave can put its data onto the master's receive line. Only receiving of data from the master is possible. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. The selected slave then switches its MRSTx line to output, until it gets a deselection signal or command. The slaves use open drain output on MRSTx. This forms a Wired-AND connection. The receive line needs an external pullup in this case. Corruption of the data on the receive line sent by the selected slave is avoided, when all slaves which are not selected for transmission to the master only send ones (‘1’). Since this high level is not actively Data Sheet 263 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces driven onto the line, but only held through the pullup device, the selected slave can pull this line actively to a low level when transmitting a zero bit. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. After performing all necessary initializations of the SSCx, the serial interfaces can be enabled. For a master device, the alternate clock line will now go to its programmed polarity. The alternate data line will go to either '0' or '1', until the first transfer will start. After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit. When the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register SSCxTB. This value is copied into the shift register (which is assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the MTSRx line on the next clock from the baudrate generator (transmission only starts, if SSCxEN=’1’). Depending on the selected clock phase, also a clock pulse will be generated on the SCLKx line. With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRSTx. This “exchanges” the transmit data with the receive data. Since the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master's shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. After the preprogrammed number of clock pulses (via the data width selection) the data transmitted by the master is contained in all slaves’ shift registers, while the master's shift register holds the data of the selected slave. In the master and all slaves the content of the shift register is copied into the receive buffer SSCxRB and the receive interrupt flag SSCxRIR is set. A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at pin MRSTx, when the content of the transmit buffer is copied into the slave's shift register. It will not wait for the next clock from the baudrate generator, as the master does. The reason for this is that, depending on the selected clock phase, the first clock edge generated by the master may be already used to clock in the first data bit. So the slave's first data bit must already be valid at this time. Note: On the SSCx always a transmission and a reception takes place at the same time, regardless whether valid data has been transmitted or received. This is different eg. from asynchronous reception on ASC. The initialization of the SCLKx pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other receivers. The state of the internal alternate output lines is '1' as long as the SSCx is disabled. This alternate output signal is ANDed with the respective port line output latch. Enabling the SSCx with an idlelow clock (SSCxPO=’0’) will drive the alternate data output and (via the AND) the port pin SCLKx immediately low. To avoid this, use the following sequence: Data Sheet 264 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces • select the clock idle level (SSCxPO=’x’) • load the port output latch with the desired clock idle level • switch the pin to output • enable the SSC (SSCxEN=’1’) • if SSCxPO=’0’: enable alternate data output The same mechanism as for selecting a slave for transmission (separate select lines or special commands) may also be used to move the role of the master to another device in the network. In this case the previous master and the future master (previous slave) will have to toggle their operating mode (SSCxMS) and the direction of their port pins (see description above). 16.2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both pins MTSRx and MRSxT of each device, the clock line is connected to the SCLKx pin. The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. Similar to full duplex mode there are two ways to avoid collisions on the data exchange line: • only the transmitting device may enable its transmit pin driver • the non-transmitting devices use open drain output and only send ones. Since the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (MRSTx for a master device, MTSRx for a slave). By these means any corruptions on the common data exchange line are detected, where the received data is not equal to the transmitted data. Data Sheet 265 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Figure 16-6 xHalf Duplex Configuration (valid for SSC0 and SSC1) Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCxTB is empty and ready to be loaded with the next transmit data. If SSCxTB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission will start without any additional delay. On the data line there is no gap between the two successive frames. Eg. two byte transfers would look the same as one word transfer. This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer. It is just a matter of software, how long a total data frame length can be. This option can also be used eg. to interface to byte-wide and word-wide devices on the same serial bus. Note: Of course, this can only happen in multiples of the selected basic data width, since it would require disabling/enabling of the SSCx to reprogram the basic data width on-the-fly. Data Sheet 266 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Port Control The SSCx uses three pins of Port 3 to communicate with the external world. The operation of these pins depends on the selected operating mode (master or slave). In order to enable the alternate output functions of these pins instead of the general purpose I/O operation, the respective port latches have to be set to '1', since the port latch outputs and the alternate output lines are ANDed. When an alternate data output line is not used (function disabled), it is held at a high level, allowing I/O operations via the port latch. The direction of the port lines depends on the operating mode. The SSCx will automatically use the correct alternate input or output line of the ports when switching modes. The direction of the pins, however, must be programmed by the user, as shown in the tables. Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand-shaking or slave select lines. In this case it is not always necessary to switch the direction of a port pin. 16.3 Baud Rate Generation The serial channel SSCx has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. The baud rate generator is clocked with the CPU clock divided by 2 (fCPU/2). The timer is counting downwards and can be started or stopped through the global enable bit SSCxEN in register SSCxCON. Register SSCxBR is the dual-function Baud Rate Generator/Reload register. Reading SSCxBR, while the SSCx is enabled, returns the content of the timer. Reading SSCxBR, while the SSCx is disabled, returns the programmed reload value. In this mode the desired reload value can be written to SSCxBR. Note: Never write to SSCxBR, while the SSCx is enabled. The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baudrate: fCPU fCPU BSSC = SSCBR = ( 2 * ( + 1) 2 * BaudrateSSC )-1 represents the content of the reload register, taken as unsigned 16-bit integer. The maximum baud rate that can be achieved when using a CPU clock of 36 MHz is 18 MBaud in SSCx Master Mode (= ’0d’), while in SSCx Slave Mode the maximum baud rate is 9 MBaud (= ’1d’; - =’0d’ is not allowed in Data Sheet 267 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces Slave Mode ). The minimum ( = ’FFFFH’ = ’65535D’). 16.4 baud rate is 274.66 Baud Error Detection Mechanisms The SSCx is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes, while Transmit Error and Baudrate Error only apply to slave mode. When an error is detected, the respective error flag is set. When the corresponding Error Enable Bit is set, also an error interrupt request will be generated by setting SSCxEIR (see figure below). The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error flags are not reset automatically (like SSCxEIR), but rather must be cleared by software after servicing. This allows servicing of some error conditions via interrupt, while the others may be polled by software. Note: The error interrupt handler must clear the associated (enabled) errorflag(s) to prevent repeated interrupt requests. A Receive Error (Master or Slave mode) is detected, when a new data frame is completely received, but the previous data was not read out of the receive buffer register SSCxRB. This condition sets the error flag SSCxRE and, when enabled via SSCxREN, the error interrupt request flag SSCxEIR. The old data in the receive buffer SSCxRB will be overwritten with the new value and is unretrievably lost. A Phase Error (Master or Slave mode) is detected, when the incoming data at pin MRST (master mode) or MTSR (slave mode), sampled with the same frequency as the CPU clock, changes between one sample before and two samples after the latching edge of the clock signal (see “Clock Control”). This condition sets the error flag SSCxPE and, when enabled via SSCxPEN, the error interrupt request flag SSCxEIR. A Baud Rate Error (Slave mode) is detected, when the incoming clock signal deviates from the programmed baud rate by more than 100%, ie. it either is more than double or less than half the expected baud rate. This condition sets the error flag SSCxBE and, when enabled via SSCxBEN, the error interrupt request flag SSCxEIR. Using this error detection capability requires that the slave's baud rate generator is programmed to the same baud rate as the master device. This feature detects false additional, or missing pulses on the clock line (within a certain frame). Note: If this error condition occurs and bit SSCxAREN=’1’, an automatic reset of the SSCx will be performed in case of this error. This is done to reinitialize the SSCx, if too few or too many clock pulses have been detected. Data Sheet 268 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces A Transmit Error (Slave mode) is detected, when a transfer was initiated by the master (shift clock gets active), but the transmit buffer SSCxTB of the slave was not updated since the last transfer. This condition sets the error flag SSCxTE and, when enabled via SSCxTEN, the error interrupt request flag SSCxEIR. If a transfer starts while the transmit buffer is not updated, the slave will shift out the 'old' contents of the shift register, which normally is the data received during the last transfer. This may lead to the corruption of the data on the transmit/receive line in half-duplex mode (open drain configuration), if this slave is not selected for transmission. This mode requires that slaves not selected for transmission only shift out ones, ie. their transmit buffers must be loaded with 'FFFFH' prior to any transfer. Note: A slave with push/pull output drivers, which is not selected for transmission, will normally have its output drivers switched. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. IRQ16_STA SSCEIR Figure 16-7 Error Interrupt Control (valid for SSC0 and SSC1) Data Sheet 269 2003-03-31 INCA-D PSB 21473 The High-Speed Synchronous Serial Interfaces 16.5 SSCx Interrupt Control The SSC0 and SSC1 (SSCx) can generate three different interrupts: SSCxTINT (transmit), SSCxRINT (receive), and SSCxEIR (error). SSCxTINT and SSCxRINT are connected to dedicated interrupt nodes. SSCxEIR is handeled by the combined interrupt COMB2INT (register IRQ14_STA). For a description of the interrupt structure refer to chapter "Interrupt System Structure" on page 8-85. Register SSCxTIC controls the transmit interrupt and register SSCxRIC controls the receive interrupt. The cause of an error interrupt request (receive, phase, baudrate, transmit error) can be identified by the error status flags in control register SSCxCON. Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields (chapter "Interrupt Control Registers" on page 899) Data Sheet 270 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller 17 IOM-2 Handler, TIC/CI Handler and HDLC Controller 17.1 IOM2 Handler One task of the IOM handler is to establish a communication path from DSP to the line interface and vice versa. Beside that function, it handles also the data transfer between line transveiver, HDLC controller and TIC/CI channel handler. Additionally, it provides CPU access to all IOM-2 timeslots via the four controller data access (CDA) register and the IOM-2 Data Transfer Unit. The PCM data of the controller data access (CDA) registers and the IOM-2 Data Transfer Unit can be configured by programming the corresponding time slot and data port selection registers. The IOM-2 handler provides access to the following blocks: • • • • • DSP Transceiver C/I channel handler (C/I0,C/I1) TIC bus handler and HDLC controller The following Figure 17-1 shows the architecture of the IOM-2 handler. Data Sheet 271 2003-03-31 272 x,y = 1 or 2 IOMHAND.VSD TO DSP DD DU CDA21 CDA20 CDA11 MSTI ASTI STI MCDA CDA_CRx CDA_TSDPxy Register CDA10 Control IOM_CR Data Access (TSDP, DPS, EN, SWAP, TBM, MCDA, STI) C D A D a ta CDA Access (CDA) Controller Data IOM-2 Handler Unit UCIF Disable (TIC_DIS) Transfer TIC IOM_CR TIC Bus IOM2 (EN, OD) CI0 IOM-2 Interface B u s D a ta Data Sheet T IC B u s D a ta 17.1.1 C I0 D a ta DU DD FSC DCL BCL C I1 D a ta Control D /B 1 /B 2 D a ta CI1 HDLC FIFO HCI_CR C/I1 HDLC D-, BData Data (DPS,EN) (EN) Control DD DU C /IO - D a ta Control B 1 /B 2 /D - D a ta TR_CR TR_TSDP_B2 TR_TSDP_B1 Transceiver Data Access (TSS, DPS, EN) TR_B1_X T ra n s c e iv e r D a ta (T R ) TR_B2_R TR_B1_R TR_D_R TR_B2_X TR_D_X INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller •. Figure 17-1 Architecture of the IOM-2 Handler IOM-2 Interface The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The FSC signal is generated by the receive DPLL (Adjust Unit) which synchronizes to the received line frame. The DCL and the BCL 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller output clock signals synchronize the data transfer on both data lines. The DCL is twice the bit rate, the BCL output rate is equal to the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled at the falling edge of the second clock cycle. The FSC signal is an 8 kHz frame sync signal. With DCL = 1.536 MHz, 3 channels of 4 timeslots are available. The frame structure on the IOM-2 data ports (DU,DD) is shown in figure 17-2. • Channel 0 Channel 1 D U B1 IOM-2 D D B2 MON0 D CI0 DASL Layer2 B1 B2 MON 0 DASL IOM-2 Layer1 Layer1 MR MX D CI0 Layer2 Channel 2 MR MX MR MX IC1 IC2 MON 1 CI1 BAC TAD IC3 IC4 CC TICBus Receive MR MX IC1 IC2 MON 1 Transmit CI1 S/G A/B IC3 IC4 CC IOMFRAME.vs d Figure 17-2 IOM-2 Frame Structure • Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of the layer-1 transceiver. • Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR and command/indicate channel (MON1, CI1) to program transfer data to other IOM-2 devices. • Channel 2 is used for the TlC-bus access. Additionally channel 2 supports further IC3, IC4 and CC channel. 17.1.2 Controller Data Access (CDA) With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the IOM2 handler provides one solution for the CPU to access the IOM-2 time slots.The functional unit CDA (controller data access) allows with its control and configuration registers Data Sheet 273 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller • looping of up to four independent PCM channels from DU to DD or vice versa over the four CDA registers • shifting of two independent PCM channels to another two independent PCM channels on both data ports (DU, DD). Between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. If this is not the case a switching function is performed. • monitoring of up to four time slots on the IOM-2 interface simultaneously • CPU read and write access to each PCM timeslot The access principle which is identical for the two channel register pairs CDA10/11 and CDA20/21 is illustrated in figure 17-3. The index variables x,y used in the following description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names has been omitted for simplification. • TSa TSb DU Control Register CDAx0 0 1 1 1 Time Slot Selection (TSS) Enable input output (EN_I1) (EN_O1) Input Swap (SWAP) 1 1 1 CDAx1 1 0 1 CDA_TSDPx2 1 0 Data Port Selection (DPS) Time Slot Selection (TSS) CDA_CRx 0 Enable output input (EN_O0) (EN_I0) Data Port Selection (DPS) CDA_TSDPx1 1 DD TSa TSb IOM_HAND.FM4 x = 1 or 2; a,b = 0...11 Figure 17-3 Access principle to CDA registers To each of the four CDAxy data registers a TSDPxy register is assigned by which the time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a time slot can be selected. With the DPS (Data Port Selection) bit the output of the CDAxy register can be assigned to DU or DD respectively. The time slot and data port for the output of CDAxy is always defined by its own TSDPxy register. The input of CDAxy depends on the SWAP bit in the control registers CRx. Data Sheet 274 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output of the CDAxy register is defined by its own TSDPxy register. If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is defined by the TSDP register of CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output timeslots are not affected by SWAP. The input and output of every CDAxy register can be enabled or disabled by setting the corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is disabled the output value in the register is retained 17.1.2.1 Looping and Shifting Data Figure 17-4 gives examples for typical configurations with the above explained control and configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers TSDPxy or CDAx_CR: a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = 0) b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP = 1) c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd and looping from DD to DU respectively Data Sheet 275 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller a) Looping Data TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 TSc ’1’ TSd ’1’ .TSS: TSa TSb .DPS ’0’ ’0’ .SWAP ’0’ DU DD ’0’ b) Shifting Data TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 DU DD .TSS: TSa TSb .DPS ’0’ ’1’ .SWAP ’1’ c) Switching Data TSa TSb CDA10 CDA11 TSc ’0’ TSd ’1’ ’1’ TSc TSd CDA20 CDA21 DU DD .TSS: TSa TSb .DPS ’0’ ’0’ .SWAP ’1’ TSc ’1’ TSd ’1’ ’1’ Figure 17-4 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) Data c) Shifting and Looping Data Data Sheet 276 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller Figure 17-5 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. . FSC DU TSa TSa µC *) DD TSa STOV ACK WR RD STI CDAxy TSa *) if access by the µC is required Figure 17-5 Data Access when Looping TSa from DU to DD Figure 17-6 shows the timing of shifting data from TSa to TSb on DU(DD) asuming an example with 12 timeslots per FSC frame. In Figure 17-6a) shifting is done in one frame because TSa and TSb didn’t succeed directly to one another (a = 0...9 and b ≥ a+2). In figure 17-6b) shifting is done from one frame to the following frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). At looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and STOV are explained in the section ’Synchronous Transfer’. If there is no controller intervention the looping and shifting is done autonomously. Data Sheet 277 2003-03-31 INCA-D PSB 21473 IOM-2 Handler, TIC/CI Handler and HDLC Controller • a) Shifting TSa → TSb within one frame (a,b: 0...11 and b ≥ a+2) FSC DU (DD) TSa TSa TSb µC *) STI STOV ACK WR RD STI CDAxy b) Shifting TSa → TSb in the next frame (a,b: 0...11 and (b = a+1 or b